I was learning verilog hardware description language. I was confused a bit with the blocking and non-blocking statements. Can someone tell me what the following verilog codes realize and simple hints how
always@(posedge clk)
begin
q1=d;
q2<=q1;
q3=q2;
end
always@(posedge clk)
begin
q1<=d;
q2<=q1;
q3=q2;
end
These are two different codes implemented separately. I think FF comes into the picture because of edge detection. But I don't understand what it realizes as it has a intermix of blocking and non-blocking statements