I have an "interesting" problem.

The proposed design, for a system I'm working on, needs to use 16x 16-bit serial ADCs and I need to interface the results of all 16 ADCs to a synchronous serial stream running at 40 Mbits per second. There will be a frame size of 289 bits comprising: -

  • A 17-bit header followed by
  • 16x 17-bits of ADC values

17 bits are allocated per ADC even though the ADCs are 16 bit. This means a frame rate of 7.225 microseconds. Fairly easy using an EPLD from the normal vendors.

By the way, the 17th bit inverts the LSB of each ADC to keep the data scrambler ticking over - it reduces "dead" periods in the data stream by about 50%. Also note that the 16x ADCs are "converted" simultaneously (an important part of the spec).

The problem starts when you look at potential ADCs - most take about a microsecond or two (e.g.) to "convert" leaving approximately 5 microseconds to stream the data from them and this is the root of the problem. In those 5 microseconds we would need to extract 16x 16 bits of data, add the extra 17th bit on and this means we would need to transmit (in order to avoid stupifying EPLD complexity), at a data rate (for those 5 microseconds) of 54.4 Mbits per second. It has to be 40 Mbits per second unfortunately (damn those bureaucrats)!

So, what I'm looking for, are ideas and hence the title of the question - If we extract the data from the 16x ADCs and stream it in a serial "holding" register, when that is complete we can transmit at the more leisurely pace of 40Mbits per second. This, as I see it requires a serial shift register that is 272 bits long (16 x 17) that once full is instantly transferred (parallel mode) to an identical shift register for outputting the data at a more constant rate. One shift register fills at one rate whilst the other is transmitting the previously stored data.

So my main question is - does such a device exist and if not, what are people's recommendations - maybe use a bespoke EPLD to do this. It would need at least 544 flip-flops of course and this is bigger than most EPLDs. I've considered (for about ten minutes) using an FPGA but power drain might be a serious issue on this design. Most of these designs I do are powered across "a gap" because the module fixes to rotating machines.

This is not my specific area of expertise (analogue is my area really) so if I've missed an obvious solution please be kind. There are a couple of ADCs that can just about convert in about 400ns but these are rare devices and expensive and physically a bit bigger than an 8-pin MSSOP. All 16-bit ADCs that fit the bill in size and cost (i.e. under $20 each and little 8-pin devices) take over a microsecond to convert.

  • 2
    \$\begingroup\$ There are plenty of low-power FPGAs. Actel (now Microsemi), in particular, has some nice ones. \$\endgroup\$ – Dave Tweed Dec 13 '13 at 0:17
  • \$\begingroup\$ @davetweed thanks pal. I'll take a look on Monday. Are they good for the sort of speed I'm looking at though? \$\endgroup\$ – Andy aka Dec 13 '13 at 0:21
  • \$\begingroup\$ Have you considered Mux to Sigma Delta ADC with a FIFO? \$\endgroup\$ – user34084 Dec 13 '13 at 6:17
  • \$\begingroup\$ Andy, the last paragraph intrigues me. Are you saying that you intend to use ADCs that come in 8-bit packages? If so, how do you get the data out of them...SPI or I2C? The first part of your question lead me to think that you had 16-bit parallel outputs, a different matter altogether. \$\endgroup\$ – Joe Hass Dec 13 '13 at 11:44
  • \$\begingroup\$ @JoeHass 8 or 10 pin packs with SPI bus is what we normally use - there isn't enough room to have byte-wide parallel packages. The LTC1403A (14 bit) does exactly what we want but it's only 14 bits. It needs only about 40ns to acquire. The limit we have (for continuous clocking out of data is about 400ns) but trying to find one is proving difficult hence the question. \$\endgroup\$ – Andy aka Dec 13 '13 at 12:03

There are plenty of low-power FPGAs. Actel (now Microsemi), in particular, has some nice ones.

I once used one of their products (sorry, I forget precisely which) in a battery-operated headset project that needed to funnel several channels of digital audio between multiple ADCs and DACs and a DSP chip. The client was quite happy with how it worked out.

| improve this answer | |
  • \$\begingroup\$ Cheers Dave, we've decided to go down this route using the IGLOO FPGA. \$\endgroup\$ – Andy aka Jan 31 '14 at 16:22

This seems to be an ideal application for an FPGA. Even a relatively small FPGA could support 16 distinct SPI interfaces to the ADCs, and creating a 289-bit shift register is pretty easy. The choice of a particular FPGA will depend on other design constraints, such as available voltages, power limits, physical size, and cost. I've hacked together SPI interfaces for both an ADC and a DAC using Verilog. 40MHz is also not a particularly high frequency for modern FPGAs.

| improve this answer | |
  • \$\begingroup\$ Thanks Joe, it's starting to look this way. Voltages avaialble are 5V but can be reduced to 3V3 and a core voltage no problem. Already got an EPLD to do the framing so I could migrate that over to the FPGA. I gotta watch power though. I reckon 150mA tops is all I've got at 3V3. There will be up to ten of these modules and my power limit is probably about 2A at 5V for all ten. \$\endgroup\$ – Andy aka Dec 13 '13 at 13:18

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.