I have an "interesting" problem.
The proposed design, for a system I'm working on, needs to use 16x 16-bit serial ADCs and I need to interface the results of all 16 ADCs to a synchronous serial stream running at 40 Mbits per second. There will be a frame size of 289 bits comprising: -
- A 17-bit header followed by
- 16x 17-bits of ADC values
17 bits are allocated per ADC even though the ADCs are 16 bit. This means a frame rate of 7.225 microseconds. Fairly easy using an EPLD from the normal vendors.
By the way, the 17th bit inverts the LSB of each ADC to keep the data scrambler ticking over - it reduces "dead" periods in the data stream by about 50%. Also note that the 16x ADCs are "converted" simultaneously (an important part of the spec).
The problem starts when you look at potential ADCs - most take about a microsecond or two (e.g.) to "convert" leaving approximately 5 microseconds to stream the data from them and this is the root of the problem. In those 5 microseconds we would need to extract 16x 16 bits of data, add the extra 17th bit on and this means we would need to transmit (in order to avoid stupifying EPLD complexity), at a data rate (for those 5 microseconds) of 54.4 Mbits per second. It has to be 40 Mbits per second unfortunately (damn those bureaucrats)!
So, what I'm looking for, are ideas and hence the title of the question - If we extract the data from the 16x ADCs and stream it in a serial "holding" register, when that is complete we can transmit at the more leisurely pace of 40Mbits per second. This, as I see it requires a serial shift register that is 272 bits long (16 x 17) that once full is instantly transferred (parallel mode) to an identical shift register for outputting the data at a more constant rate. One shift register fills at one rate whilst the other is transmitting the previously stored data.
So my main question is - does such a device exist and if not, what are people's recommendations - maybe use a bespoke EPLD to do this. It would need at least 544 flip-flops of course and this is bigger than most EPLDs. I've considered (for about ten minutes) using an FPGA but power drain might be a serious issue on this design. Most of these designs I do are powered across "a gap" because the module fixes to rotating machines.
This is not my specific area of expertise (analogue is my area really) so if I've missed an obvious solution please be kind. There are a couple of ADCs that can just about convert in about 400ns but these are rare devices and expensive and physically a bit bigger than an 8-pin MSSOP. All 16-bit ADCs that fit the bill in size and cost (i.e. under $20 each and little 8-pin devices) take over a microsecond to convert.