I have a big challenge in my design to overcome:
I need clock frequency accuracy of <0.2ppm with incredibly low power consumption.
What we are doing currently is, using a 3G transceiver' baseband output, we are using a PLL using the baseband as the control signal, and frequency multiplying from there, and achieving incredible results (<1ppb!!!), however the power consumption is too high, and this level of accuracy is not needed. The transceiver's current is around 26mA.
I am thinking, is there any form of clock synchronization technique that does not need a constant control signal? Could a control signal of some kind be intermittently 'injected' into the system so re-synchronize the clock at set intervals? I'm thinking of powering on and off the transceiver at a low duty cycle (5% on, 95% off type of thing), to reduce power consumption in this way.
My understanding is a little limited, but from what I already know this would be difficult (impossible) using PLLs due to the lack of a constant control signal.
I'm thinking what if the control signal input could be switched from the PLLs output itself and the baseband output of the 3G transceiver?
The basic concept of what I need is shown below: Please ignore where it says 'OCXO'. It should say '3G Tranceiver Baseband'.
Any constructive suggestions are welcome; no "it can't be done" replies please.
Crystal oscillators are not really an option due to at least one or a variation of power consumption, size and device cost.