Clocked edge-triggered timing (contamination delay)

Question

I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is assumed to be greater than its hold time, "giving it the important property that its inputs and outputs can be read and written simultaneously (that is, by similar devices sharing the same clock input)".

But I didn't quite understand this statement. As far as I know (I'm very new to this subject), contamination delay is a minimum time, measured after the active clock edge, during which the output remains valid after the input has changed (measured after the active clock edge), and hold time is a minimum time requirement measured from the active clock edge, during which the input data has to be kept stable. Why is contamination delay of register greater than the hold time, and how exactly does this fact allow it to be read and written simultaneously? Could someone give a more detailed explanation?

Update: I understand basically the importance of having contamination delay greater than the hold time in edge-triggered flip-flop in the situation where there are two chained flip-flops (that is, the output of the first one serves as input to the second one). When clock rises, the input to the first flip-flop gets sampled and propagates to the second flip-flop. Then, after one clock period, when clock rises again, the second flip-flop samples its input. But the input of the second flip-flop must remain at the same value for at least a hold time after the clock rises, if we want it to get correctly stored. So, the first flip-flop must guarantee that its output (which is the input for the second flip-flop) will not change for at least a hold time. That is, the contamination delay of the first flip-flop must be at least the hold time of the second flip-flop.

Is this correct? The part that I'm not understanding is why this fact gives to registers "the important property that its inputs and outputs can be read and written simultaneously (that is, by similar devices sharing the same clock input)".

Answer 1

From my textbook, Digital Design and Computer Architecture, Harris and Harris, pg. 88

An important note

When you are attempting to find the propagation delay of a combinational circuit with multiple elements, you must add the propagation delay through the critical path.

However when you are attempting to find the contamination delay of a combinational circuit with multiple elements, you must add the contamination delay through the shortest path.

That much is probably obvious to you.

Actually, it sounds to me like you are referring to contamination delay. You said contamination delay is the amount of time measured after an input changes that the output remains valid. If you mean the previous output, then yes, because that means the same thing as until the output begins changing to the new value.

Addition

About your question as to how this deals with reading and writing from a register. This confused me for awhile, but I think it makes perfect sense to me now.

So what you said about contamination delay and hold time is correct. This problem applies to when flip-flops are daisy chained. And if you think about it, it also only applies to when you want to read and write at the same time.

Imagine a circuit with just 2 flip flops. It doesn't necessarily have to be a register, just that the first flip-flop is the storage element that is written to, and the 2nd flip-flop is the storage element that reads the first one. If you only needed to read and write on different clock cycles, then none of this delay stuff would matter, because reading would always occur on a different clock cycle when the output of the first was stable, and couldn't change since writing can't occur in the same clock cycle.

However if you wanted to write a new value to the 1st flip-flop, as well as read the previous value properly into the 2nd on the same clock cycle, then that is the exact situation you described, where if the contamination delay of the first was less than the hold time of the second, then writing to the first would thereby contaminate the reading of the second. It makes perfect sense. The read has to occur successfully before the write begins to change what's being read, or else the value gets lost.

Answer 2

I've never heard the term "contamination delay" before, but it sounds like you're talking about the input hold time requirements.

Edge-triggered storage devices have a time window relative to the clock edge during which the input must be held stable in order to reliably capture its value (and avoid metastability issues). The start of this window is called "input setup time" and the end of the window is called "input hold time". Input hold time is often zero, and can even be negative.

The output of such a device has a time window during which it will change if the new value is different from the old value. There is usually a minimum clock-to-output time, also called "output hold time", which is always some small positive value. There's also a maximum clock-to-output propogation time, after which the output is guaranteed to have the new value.

Your question relates to the relationship between the output hold time and the input hold time. As long as the former is larger than the latter, strings of identical devices (e.g., flip-flops in a shift register) can be connected directly together, output to input, with no concerns about unexpected behavior.

Answer 3

I think the term "contamination delay" is used to refer to the minimum possible duration between when the inputs cease to hold their old valid input levels and the earliest moment when the outputs might cease to hold their old valid output levels. The term "minimum propagation delay" is often used for this purpose, but such usage implies that the term "propagation delay" actually measures two things:

• The amount of time between when an input first ceases to be a valid representation of the old level, and when the output is first allowed to case to be a valid level.

• The amount of time between when an input assumes a stable valid logic level, and the time by which the output is required to have assume a stable logic level.

If one assumes that an input will simultaneously cease to be a valid low and become a valid high, or vice versa, the starting reference for these two times will be the same. In some cases, however, they may be different. Further, the term "propagation delay" generally implies that something useful is being propagated, but in some cases an input stimulus may cause an output which was valid, and which should remain in its present state, to become momentarily invalid before returning to the state it had held previously.

Imagine, for example, a circuit which is supposed to output "high" when an 16-bit ripple ripple counter has a value from 32767 to 65534, inclusive. Ideally, the circuit would start outputting a "high" precisely on the arrival of the 32,767th pulse (assuming the counter started at zero) and go low on the arrival of the 65,535th pulse. Absent some extra circuitry, however, the circuit may very well go low briefly with the arrival of the 32,768th pulse (when it should just sit high), and go high briefly with the arrival of the 65,536th pulse (when it should just sit low). Depending upon what the "compare" output is doing, the fact that it briefly becomes invalid on those pulses may or may not be an issue, but it would seem a little awkward to think of its behavior in terms of "minimum and maximum propagation time". In all the cases where the output is supposed to change, it will do so after a flop delay and a couple gate delays. In some cases where it isn't supposed to change, however, it will do so anyway and will remain in the wrong state for 16 flop delays (much longer than the time required for a "proper" switch). A term like "contamination delay" may be more suitable for that.