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I was given the following Op-Amp circuit to analyse and to find the potential V_out as a function of time, with V_in defined as the Heaviside step function:

$$V_{\text{in}}=\begin{cases}0\mathrm{V} & t<0 \\ 1\mathrm{V} & t \geq0\end{cases}$$

schematic

simulate this circuit – Schematic created using CircuitLab

I first begin by finding Vo as a function of V_in, by equating currents and using that the current going into the inverting input of OA1 must be 0A:

$$\frac{V_{\text{in}}}{R}=C\frac{\mathrm{d}V_{0}}{\mathrm{d}t}\implies V_{0}=\frac{1}{RC}\int_{-\infty}^{t'}V_{\text{in}}\:\mathrm{d}t$$

Then again at OA2:

$$\frac{V_{\text{out}}}{R}=\frac{V_0}{R}+\frac{V_{\text{ref}}}{R} \implies V_{\text{out}}=V_0+V_{\text{ref}}$$

Combining the two equations gives:

$$V_\text{out}=\frac{1}{RC}\int_{-\infty}^{t'}V_{\text{in}}\:\mathrm{d}t+V_{\text{ref}}$$

When we use V_in as defined above and with R = 100kΩ, C = 10µF and V_ref = 10V, we get:

$$V_{\text{out}}=\begin{cases}(t+10)\mathrm{V} & t\geq0 \\ 10\mathrm{V} & t<0\end{cases}$$

However, this means that we end up with:

$$\lim_{t\to\infty}V_{\text{out}}=\infty\mathrm{V}$$

Which suggests that I've done something very wrong here? Or is this just a consequence of using the ideal Op-Amp assumption?

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  • \$\begingroup\$ What happens if you assume an ideal voltage-limited op-amp (say, rail-to-rail)? \$\endgroup\$ – John Dvorak Dec 15 '13 at 17:48
  • \$\begingroup\$ @JanDvorak I'm not sure how I'd go about modelling that? I would no longer be able to assume that the current input would be zero? \$\endgroup\$ – Thomas Russell Dec 15 '13 at 17:52
  • \$\begingroup\$ You can assume that either the input difference is zero and the outut is within rails, or that the output is railed and the input difference has the appropriate sign. The input current is zero in any case, and so is the output impedance. \$\endgroup\$ – John Dvorak Dec 15 '13 at 17:57
  • \$\begingroup\$ If you mean the current at $V_in$... yeah, that's no longer proportional to $V_in$ when the first op-amp saturates. That shouldn't pose too much challenge, however, as what remains is a simple R-C circuit (that OA2 doesn't even see) \$\endgroup\$ – John Dvorak Dec 15 '13 at 18:01
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You haven't done anything wrong. The first stage of your circuit is an integrator, and when you integrate a step function (your input) you get a ramp. Since your input never ends, the ramp never ends and the final value is infinity.

Of course, this only holds for an ideal op-amp. In a real op-amp, output voltages would be limited to the rail voltage.

In case you're wondering, I've never seen the output voltage limitations accounted for in equations. You just have to introduce a nonlinear element into the model (a voltage limiter) and then all of your linear equations are essentially out the window. In other words, the linear equations you're used to are all well and good as long as the output of any of your stages doesn't exceed the rail voltage - as it will in this case.

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