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I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package.

The design is also almost complete, however at the moment it will no longer fit in the FPGA. I can turn off parts to get it to fit, however I need to reduce the resource usage in order to complete the design and have it meet timing and size requirements.

I would like to know if there are any tools our reports that can help me identify which parts of my design are consuming the most resources. My design is not partitioned, and is split over about a dozen or more VHDL modules.

Xilinx timing reports are fantastic, but now I need to know where I can get my best bang-for-buck in terms of space saving.

I also have a hard time telling which type of resources I'm running out of, or what effects those resources.

Another annoyance is that as the design gets larger, components that used to meet timing are starting to fail because their placement is no longer as ideal.

Currently, I use the Post-Place and Route Static timing reports, and I use SmartXplorer. I'm using design strategies to optimize for timing.

After turning off part of my design to get it to fit, here are some of the results:

slice register utilization: 42% slice LUT utilization: 96% number of fully used LUT-FF pairs: 38% Does this mean I'm light on registers, but heavy on gate usage?

Are there tools to help developers optimize for area, or at least give them more insight into their code?

Update: After looking at the Module Level Utilization, I found out that I had small glue async fifos all over the place that take up about 30% of the total LUTs. I am using them as cross-clock-domain glue for high speed buses. I should be able eliminate these, since the clocks are tightly related. (120 MHz input, produces 100 MHz and 200 MHz through DCMs)

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  • \$\begingroup\$ It looks like you have a lot of interconnections between the signals, I am sure you can fix that by changing the levels of optimization, resource sharing and such. What tool are you using? ISE or Vivado? \$\endgroup\$ – FarhadA Dec 17 '13 at 14:16
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    \$\begingroup\$ I'm using ISE (Vivado won't support Spartan-6) I cross-posted this in the Xilinx forums, and they said to turn on Detailed Map Report. I did this, and the *.mrp file now contains Section 13 - Utilization by Hierarchy. I'll post the data once I get it formatted better. \$\endgroup\$ – Marcus10110 Dec 17 '13 at 21:07
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I cross posted this question on the Xilinx Forum here: http://forums.xilinx.com/t5/Implementation/How-to-determine-what-part-of-the-design-consumes-the-most/td-p/393247

This answer is largely based on the comments there. Thanks to Deepika, Sikta and Gabor.

First, enable 'Generate Detailed MAP Report' in the map process properties (-detail).

Then, open the Design Summary, and navigate to Module Level Utilization. Here is the complete hierarchy, showing exclusive and inclusive design utilization.

Each line will show a number pair like 0/5392. This means that that module contains zero of that specific element, but that module and all of its sub-modules contain a total of 5392 elements.

Here is my output (partially expanded) Utilization report http://i41.tinypic.com/axedjm.jpg

When working on reducing the size, Gabor recommends switching to a larger FPGA in the synth tools so that it can completely map even when it's too large to fit in your current FPGA, and it will make the tools run faster.

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Looks like you are using up almost all of the logic resources while only using half of the registers. It looks like you need to figure out what is eating up all of your LUTs. There are ways to optimize particular components and make them a bit more space efficient - things like RAMs, shift registers, and state machines. Look at the resulting .log file from the synthesizer. It will tell you what sort of components are being inferred. Make sure that it is inferring components properly. If it isn't, it may not be generating a particularly efficient netlist. You can tell a lot just by looking at the synthesis log files. It's possible a few minor changes to your code will allow the syntheizer to infer various components, so take a look at the synthesizer manual for some template. You may need to switch the synthesizer over to optimize for area instead of speed. Also, check to make sure you don't have any infer settings turned off. I once tried to synthesize a design component that consumed 40% of a Spartan 3E 500 (9,312 4-input LUT/FF pairs, 5.6 KB block RAM) for a Virtex 6 HXT 565 (354,240 6-input LUT/dual FF pairs, 32 MB block RAM). It took 7 hours for Xilinx par to finish and took up about 40% of the chip. ?!?!?!? Turns out infer block RAM was turned off, and the synthesizer turned several KB of RAM into LUTs. Not the most efficient decision ever. After changing the setting, it took up like 1% of the chip. Go figure.

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It would be worthwhile posting the whole 'resource usage' section from the tool output.

Do you use all of the Block RAMs? It's common to be able to replace logic/math functions with equivalent RAM look-up tables if the domain is sufficiently restricted, and they are of sufficient complexity to be worthwhile pre-calculating.

As well as the inference of memory, the same applies for Multipliers. Sometimes a tiny deviation from the recommended instantiation template can throw out the multiplier being inferred to DSP48A units.

If you are using the PCIe controller, can you reduce the total buffer space reserved for TLP payloads, or the maximum TLP packet size? This can reduce the RAM/logic usage of the IP core at the cost of though-put/total bandwidth.

With (Altera) Quartus, you can multi-select items in the design hierarchy view and see there post-p&r area usage colour coded/clustered. This can give a visual idea of the relative usage of your design modules.

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  • \$\begingroup\$ Thanks. I'm using the hard IP macros for the multipliers and I used CoreGen to make the FIFOs, although I did select some of the small fifos to use distributed RAM (instead of block RAM). I'll look into their usage. \$\endgroup\$ – Marcus10110 Dec 17 '13 at 21:09

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