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Circuit A has a throughput of 50 Megabits/second (Mb/s) running at 33 Mhz, while Circuit B has a throughput of 70 Mb/s running at 50 Mhz. It is clear that running a circuit at a higher frequency can increase the speed of operation. But to what extent can the frequency of a circuit be increased in order to rank up its speed?

It's easy to say Circuit B outperforms Circuit A, but that is ignoring the fact that Circuit B runs at a higher frequency. A 'naive' way to account for the difference in frequencies is to normalize both circuits to run at the same frequency, say 50 Mhz in this case, which will reveal the true capabilities of the two implementations.

But it's not that straightforward is it?

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  • \$\begingroup\$ Define the circuit - is it a microprocessor? Are both the same circuit just with differing clocks? \$\endgroup\$
    – John U
    Commented Dec 19, 2013 at 16:59
  • \$\begingroup\$ This is a very broad and very vague question. It might be answerable if you specify what circuit you are talking about and what a Mb/s exactly means. \$\endgroup\$ Commented Dec 19, 2013 at 17:10
  • \$\begingroup\$ Obviously, it's not the same circuit, otherwise the question would be meaningless. I am expecting discussions along the lines of clock cycles, critical path to better understand the connection. The circuits are for a decoder for a wireless system, but I think the concept is a broad one. @JohnU \$\endgroup\$
    – Mowgli
    Commented Dec 19, 2013 at 17:10
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    \$\begingroup\$ Why "obviously"? A faster clock can slow identical systems down due to missing timing targets and entering wait-states, losing synchronisation, etc. so it's not obvious - and you should probably include more detail if you don't want generalised / broad answers. \$\endgroup\$
    – John U
    Commented Dec 19, 2013 at 17:13
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    \$\begingroup\$ Is this some sort of question from a hand-wavey book? If it is so, please indicate. Otherwise we can go too close to real life in answers. \$\endgroup\$
    – AndrejaKo
    Commented Dec 19, 2013 at 17:37

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No, it isn't. I've heard about the NXP ARM7TDMI at 60 MHz outperforming an Atmel at 72 MHz. IIRC the reason was that the Atmel had to add wait cycles for reading Flash memory. The NXP had to add wait cycles as well, but read 4 words at a time, so the wait cycles were only needed in 1 read out of 4.

Wait cycles are typical for distorting the linearity of MIPS/MHz. For instance at 30MHz you may not need wait cycles, but you may need them at 33MHz, which will probably make the 33MHz version slower.

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