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Construct an 8k X 32 ROM using 2k X 8 ROM chips and any additional required components. Show how the address and data lines of the constructed 8k X 32 ROM are connected to the 2k X 8 chips.

I tried to solve it but I am not sure if I got the correct answer. Could anyone check my drawing and correct me?

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    \$\begingroup\$ Where does the address come in to your 2k-by-8 memories? Can you figure out how many 2k-by-8 devices you will need to give you a total of 256k bits? \$\endgroup\$
    – Joe Hass
    Dec 27, 2013 at 16:35
  • \$\begingroup\$ do i have to determine where does the adress line come from ? \$\endgroup\$
    – user34755
    Dec 27, 2013 at 16:58
  • \$\begingroup\$ i tried to answer it like what my book did to a similar problem dropbox.com/s/wz4jkae3n0q444l/bm.PNG \$\endgroup\$
    – user34755
    Dec 27, 2013 at 17:03
  • \$\begingroup\$ i am not sure if putting a 8 ships(2k*8) and 3*8 decoder is right ....... \$\endgroup\$
    – user34755
    Dec 27, 2013 at 17:07
  • \$\begingroup\$ You'll need 16 ROMs, if I've counted correctly. \$\endgroup\$ Dec 27, 2013 at 17:09

4 Answers 4

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This is a two step problem.

First Step:

Combine your 2k x 8 ROMs into a 2k X 32 ROM (requires 4 x 2k x 8 ROM ICs per 2k x 32 unit)). The address inputs will be common and need to be connected in parallel. The data outputs are kept separate to for the 32 lines required. Don't forget there are also control lines, usually a chip enable and a read line (usually active LOW) but check the specs.

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Second Step

This involves combining four "2k x 32 bit" ROM units. The input ADDRESS LINES (A0 - A10) are connected together in parallel. The OUTPUT DATA lines are also connected together in parallel. This just leaves the problem of the CONTROL LINES. The READ line is simply commoned as you want the ROM to output the data with a single 'read' signal. The CHIP ENABLE lines are used as an extra ADDRESS signal to ensure that only ONE 2k x 32 bit block is addressed at any given time. We have input addresses A11 and A12 to give the full 8K address for the ROM. We need to add a 2 to 4 line decoder to convert these address lines to CHIP ENABLE selections.

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You need to do this in two steps. Step 1: Take four 2k-by-8 ROMs and parallel connect the address lines and the output enables to make a 2k-by-32 ROM. Step 2: Take four of these 2k-by-32 ROM circuits, parallel connect their address and data lines, and connect their output enables to the output of a decoder. The decoder input is the remaining two high address lines and the output enable for the whole 8k-by-32 ROM.

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  • \$\begingroup\$ Thanks a lot BUT :( Honestly I did not learn How to solve it in two-step .I don't know how to connect the address my teacher didn't taught me I will really appreciate your help if you show me how to connect the address ??? \$\endgroup\$
    – user34755
    Dec 27, 2013 at 17:18
  • \$\begingroup\$ Each 2k-by-8 ROM chip should have 11 address pins, A0 to A10, 8 data pins, and an output enable. To "parallel connect" the address lines, connect the A0 pins on each chip together. This will be the A0 address line for the entire circuit. Repeat for A1 through A10. Each row of four chips (from step 1) will have 32 data lines, 8 from each chip, which we will refer to as D0, D1, ...D31. To parallel the data lines, connect D0 of each row together. This will become the D0 data line for the entire circuit. Repeat for D1, D2, etc. for each row. \$\endgroup\$
    – user28910
    Dec 27, 2013 at 18:52
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No, you have several problems.

For an 8k-by-32 memory, how many address lines must there be and how many parallel data lines must there be?

When constructing an 8k-by-32 memory, how many individual 2k-by-8 memories must be combined?

How many of the 2k-by-8 memories should be enabled at any given time? How do you determine which ones should be enabled?

How many address lines must go to each of the 2k-by-8 memories?

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Use 2:4 Decoder and 16 2kx8 ROM in 4x4 manner. ie, for each decoder line enable 4 number of 2kx8 ROM will be enabled.

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