I'm working on a project with the quite new STM32F429 in LQFP208 package.

I need to solder the first couple of prototype by myself for low budget reason. I choose this package so I could check myself if a problem is due to the routing/firmware or just a soldering issue.

In the project there are an LCD, a CAMERA, an ULPI and a 32b SDRAM bus plus some other slower interface.

The FMC BUS will be only used for SDRAM, no other memory is needed for the project.

The PCB stackup is a standard 4 Layer S-GND-VCC-S.

I need an advice for what would be the best approach to route the SDRAM/MCU interface.

Here there are 2 different design that could be done:


Left one will be the best to have very short traces, but it will not leave too much room for lenght matching,not really needed due to really low propagation delay for short traces). The LCD/ULPI/CAMERA bus could be routed externally whitouth much problem.

Right one could be better, slightly longer traces but lot of room for lenght matching, and still no termination needed. The LCD/ULPI/CAMERA bus will be routed externally but they will meet the SDRAM bus in lot of point so vias count will be increased on theese bus and layout will be much more complicated!


Both sides assembly is a must because of some other compontents.

Could you explain which one would you choose and why?


I choose the left one after populating the pcb, so there wasn't too much space for the right one.

This is the preliminary result.

Advice is still accepted to improove the layout:



Added Power and Ground vias:


Thank you!

  • \$\begingroup\$ Don't you want to route power and ground first? \$\endgroup\$
    – dext0rb
    Jan 3, 2014 at 23:56
  • \$\begingroup\$ It's a 4 Layer Board, decoupling caps are already placed, so I just need to put the via's and that's all! I will moove the traces if needed to make room for power vias. \$\endgroup\$
    – Leo
    Jan 4, 2014 at 0:18
  • \$\begingroup\$ Added PWR and GND via's! \$\endgroup\$
    – Leo
    Jan 4, 2014 at 0:53
  • \$\begingroup\$ Ahh missed the 4 layer thing, sorry. \$\endgroup\$
    – dext0rb
    Jan 4, 2014 at 1:18
  • \$\begingroup\$ How about your SDRAM's performance after you get this PCB? \$\endgroup\$
    – Ross
    May 28, 2019 at 4:36

3 Answers 3


I would choose the right option for ease of assembly. One sided will also be cheaper if you go to larger scale manufacturing.

The only reason I'd pick the left option would be size constraints.

  • \$\begingroup\$ Both sides assembly is a must because of some other compontents. \$\endgroup\$
    – Leo
    Jan 1, 2014 at 17:31
  • \$\begingroup\$ Talk to your PCB maker, in any case. A big RAM chip on side 2 may be different from a cap here and there, and might necessitate a gluing step. \$\endgroup\$ Jan 1, 2014 at 18:11
  • \$\begingroup\$ Components for both sides requires anyhow hand TH step and gluing for 5MP camera module! I would say that i will not care about double assembly costs! If everything will work fine with this prototype I will go for a simpler 6 Layer PCB and BGA packages for both MCU/SDRAM and FPGA! \$\endgroup\$
    – Leo
    Jan 1, 2014 at 18:16

100 MHz SDR SDRAM doesn't really require any length matching. You could easily go away with the right option. That is what I have done by the way.

  • \$\begingroup\$ Depends on trace lengths, of course. But yes, if traces are less than 2" - not an issue at all. \$\endgroup\$ Nov 8, 2019 at 12:31

I'd choose the left one, and actually I've routed it like that on my PCB the first time, but in the end I changed the design to the layout on the right but with the RAM on the bottom layer. My rules of thumb are:

  • Route all the tracks with the same amount of vias and layers: this helps in making them almost negligible in the transmission line computation. In my case, every track has one, and only, via and goes from the top layer to the bottom layer. AFAIK this is more important than having the lines length tuned.

  • Keep RAM power ports as far as possible from the MCU. This COULD be a problem during DRAM refreshes and if the connection speed is very high, as very fast current transients may lower the power supply on your STM.

  • Every power port has to have its own capacitor, with its own vias. This helps in decoupling fast transients. (I saw you did it,too!)

I may add that this is my first relatively high speed project and I'm just an EE student with experience only in power circuits. I based my answers on what I learned in university in a course I did last year.

Hope it helps, I'd like to know if your design worked: my favourite choice was the left one, but I did not chose it in the final design because of the uncertainty on the power supply issues that may (or may not!!) arise.


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