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I'd like to create a logic function that toggles with the (inverted) clock when enabled and stays low when disabled, like so:

clk ena out
 0   0   0
 1   0   0
 0   1   1
 1   1   0

I could do that with simple AND/NOT gates, like in the following schematic:

Inverted clk ANDed with ena

The output should be glitch-free though, so I thought of the following circuit instead:

Self-resetting DFF with inverted clk

To avoid out glitches, ena (which changes triggered on the rising clk edge) is sampled at the falling clk edge.

My question is about the DFF's reset input while ena is high: This will only be a very short pulse (almost like a glitch itself), from the time clk rises until the DFF is reset. Will this cause any problems or is it safe to use this circuit?

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2 Answers 2

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I don't exactly understand what your requirements are, but it seems to me that you simply want to create a "gated clock" and avoid creating malformed clock pulses when "ena" changes when clock is low (and the output clock pulse is generated). This problem is discussed in this article. One of the proposed circuits is shown below.

Please note that all circuits discussed in the linked article have some disadvantages, so you should select the proper one based on other constraints.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Looking at your schematic, I don't think the truth table I gave in the question is met... I think the REG1's CLK input needs to be inverted. Thanks for the clock gating suggestion, I'll look into it. \$\endgroup\$
    – FriendFX
    Jan 2, 2014 at 23:18
  • \$\begingroup\$ I edited your schematic to invert the clock before it feeds into REG1. See this new question for following up on the circuit issue. Thanks! \$\endgroup\$
    – FriendFX
    Jan 3, 2014 at 5:05
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I think it could cause problems, but you haven't provided enough information to know for certain one way or another. When the FF output is high and the clock goes high the reset input to the FF will start to rise. Since it is an asynchronous reset the FF output will start to fall. If the AND gate is fast then the reset input will start to fall before the FF output has fallen completely to a low level. Even worse, the output of the FF could go low long before the internal state of the FF has completely changed to a 0.

Seems to me you could end up in a metastable state or the whole thing could oscillate. You need to have precise control over the timing to make it work, and make sure that the delay through the AND function is much longer than it takes for the FF to completely reset.

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  • \$\begingroup\$ You're right, I don't want to end up with the FF being in some weird half-reset state. In your answer, you probably meant "reset input will rise before the FF output has fallen", since it is a positive reset (which I wouldn't use anyway but drawing the schematic was easier :) ) ...I guess I should put a delay between the AND's output and the FF's reset input to be safe. \$\endgroup\$
    – FriendFX
    Jan 2, 2014 at 4:11

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