# Circuit to enable (inverted) clock glitch free

This is a follow-up question to https://electronics.stackexchange.com/a/95195/13354, in which I was asking about a specific solution to the more general problem described here.

I'd like to create a logic function that toggles with the (inverted) clock when enabled and stays low when disabled, like so:

clk ena out
0   0   0
1   0   0
0   1   1
1   1   0


In addition to that, I'd like the out signal to be glitch-free, as shown in the following example waveform:

As shown in this image, potential glitches of the ena input can happen shortly after the clk edges; nevertheless, the out waveform should be glitch free.

According to this answer to aforementioned question, the circuit should be a clock gate rather than a self-resetting flip-flop. This is the proposed schematic:

simulate this circuit – Schematic created using CircuitLab

Unfortunately, this still causes glitches when ena goes low, because the Q output of the flip-flop is delayed with respect to clk (note that I ignored the common delay between clk and its inversion, which I think doesn't contribute to the issue):

Now my question: What circuit should I choose to have the out signal glitch-free?

I think, that in this case you should delay the inverted clock signal, using the even number of inverters between the CLK input of REG1 and the lower input of the AND gate.

Please note, that even in this case you may run into trouble caused by the metastability of REG1. To reduce this risk, I'd suggest to add yet one stage of synchronization of the ena signal (however of course it will slightly change the functionality, as ENA will be delayed).

simulate this circuit – Schematic created using CircuitLab

You can also try another circuits shown in the article linked in my response to your previous question, however you should keep in mind that the last and most promising one seems to be patented :-(.

• Thanks for the answer! Could you explain why there might be a metastability problem in REG1 if there is no REG2? To clarify, the glitches on ena only ever occur after a clk edge (rising or falling), therefore any clk edge sampling ena should be safe. Jan 7 '14 at 6:42
• If ena changes its state near to the active edge of the clk signal (violating the setup time and hold time requirements), the flip-flop may respond in a non-standard way, due to metastability. E.g. its propagation time may significantly increase. Addition of another synchronizing stage (REG2) decreases the risk, that the signal on D input of REG1 will violate setup time and hold time requirements (however such a risk still exists).
– wzab
Jan 23 '14 at 22:32
• Thanks for the explanation. Unfortunately I can't accept your answer as it stands because it wouldn't produce the same timing as the one I asked for. If we assume that setup and hold times of ena with respect to clk are always met, I think it is safe to remove REG2, in which case your circuit exhibits the behaviour I asked for - but only if the delay caused by NOT2 and NOT3 is big enough to "cover" the glitches, or am I missing something else? Jan 24 '14 at 0:23
• In case of metastability you always have a trade-off between the delay introduced by additional synchronizing flip-flops, and reliability of the system. Please note, that metastability may also cause a jitter of the gclk signal. If you accept this risk, you may ommit REG2
– wzab
Jan 26 '14 at 16:18
• I know about metastability problems, what I am trying to say is that I think they don't apply here because ena changes synchronously with clk, i.e. after either one of clk's edges. Therefore I think having REG2 only introduces delay while not adding anything valuable to the behaviour. Of course, if ena was asynchronous to clk, you'd use as many stages of registers as feasible to avoid metastability. Jan 27 '14 at 3:19