10
\$\begingroup\$

I have not used a DSP chip as of yet. All I know is that their architecture is such that they can carry out calculations quite fast, usually within a clock cycle, they have multiply-accumulate instructions in their instruction set and they have DMAs so the CPU does not have to waste precious time moving data around. I think there is more to it, but these are a few basic points.

I can see that Microchip has dsPIC which is their DSP chip line. Can't we just use a PIC18 or PIC32 which also has built in multipliers to do DSP as well? How is the dsPIC different from the normal PIC?

My main question is this, Why do we need to have something seperate and distinct called DSP chip and not integrate high precision floating point unit calculation capability on all the microcontrollers? Surely with the process technologies we have now, this should not take a lot of space.

Also, how do I know that I need to use a DSP chip in my project rather than a normal microcontroller>

\$\endgroup\$
1
3
\$\begingroup\$

Generally "DSP..." means 'more relevant horsepower and/or more relevant hardware at the time the product was introduced.'
Generalised processors tend to catch up with olde specialist devices.
DSPIC is p[robably 10+ years old - Olin will know.

[Items in brackets relate to some DSPIC examples - not exhaustive].

In DSP products expect some mix of:
Expect things like barrel shifters,
wide fast pipelines and fast single cycle execution times,
wide single cycle instructions,
DMA [6 or 8 channels, dual port RAM buffers] large linear memory addressing ranges [4 Mword program, 64 kB data] specialist arithmetic oriented features
Maybe:
specialist peripherals such as motor control,
hardware for several different coms standards [CAN, IIC, UART, IIS, AC97, ...] deeper than usual coms buffers [4 bytes] faster and/or wider than usual ADCs [2 Msps, 10 or 12 bit]

You'll find most of these in the DSPIC family - and increasingly so in gp processor families.
In extreme cases you get user microcoding and more.

\$\endgroup\$
3
  • 1
    \$\begingroup\$ If I remember right, I first heard about the dsPIC design effort in 1999, first samples were given out in early 2002 with production parts late 2002 or early 2003. I still somewhere have a hand-brased 30F2010 in a 28 pin ceramic DIP package that was accidentally labeled as a 30F6010. It only ran at 1/3 the eventual full speed, and was hand-marked as being #55 or something. \$\endgroup\$ Jan 4 '14 at 15:03
  • 1
    \$\begingroup\$ They can also be clocked to up to 200 or 260MHz while the PIC line only support up to 4 to 20MHz. Being 10+ times faster is definitively a point to consider. \$\endgroup\$
    – Havenard
    Feb 12 '18 at 23:04
  • 1
    \$\begingroup\$ @Havenard - Noting that this is a 2014 Q&A: He mentioned PIC32 as a possible alternative to the DSPIC. The 2007 PIC32MX has Cmax (max clock frequency) of 80 MHz. The 2013 PIC32MZ has Cmax of 252 MHz. || Useful albeit incomplete comparison here {Wikipedia}. \$\endgroup\$
    – Russell McMahon
    Feb 15 '18 at 11:36
12
\$\begingroup\$

Some of the advantages of a dsPIC over earlier-architecture PICs, like the PIC 16 and 18 families:

  1. 16 bit wide data paths and ALU, as apposed to 8.

  2. Ability to directly address (later versions of both architectures extended this in various kludgy ways) more data memory. A basic PIC 16 can address 128 bytes directly, 512 with banking. The newer PIC 16F1xxx have extended banking to allow addressing more data memory. The PIC 18 architecture is limited to 4k bytes. The dsPIC architecture can address 64k bytes or 32k 16-bit words directly, although for various reasons only half of that is available for RAM in the basic architecture. A banking scheme in some of the later models has extended that.

  3. Faster. The original 30F could run at 30 MIPs, with 40 MIPs parts the norm now. The new E series can run up to 70 MIPs, although there are more reasons it might stall waiting on something than the earlier slower models. They are still significantly faster on average.

  4. DSP capability. The DSP engine has two 40-bit accumulators and the usual hardware to perform a sequence of MAC operations on arrays one MAC per instruction cycle (see Dave Tweed's answer). The MAC and related instructions overlap array indexing and loop termination with the actual multiply-accumulate.

  5. 15 software-usable 16-bit "working registers" instead of the single 8-bit W register of the 8 bit PIC architectures.

  6. Barrel shifter.

  7. Single-cycle 16x16 --> 32 bit multiply.

  8. Hardware divide. A 32 div 16 --> 16 bit operation takes 18 cycles.

  9. Lots of 3-operand instructions. For example, you can add the contents of two working registers and put the result into a third, all in a single cycle. This applies to most math, logic, and shift operations.

  10. Overall more regular and symmetric instruction set.

  11. Vectored interrupts. The PIC 16 has a single interrupt vector, and the PIC 18 has two. On the 16 bit parts (PIC 24, dsPIC 30 and 33), each interrupt source has its own vector. This reduces latency in the interrupt routine because it doesn't have to spend cycles figuring out which interrupt to service.

    This also allows for better software architecture. The interrupt routine for a particular peripheral can be in the same module as the other code handling that peripheral, instead of having to have one global interrupt routine.

  12. Various other advantages that fall out from the wider architecture.

\$\endgroup\$
9
\$\begingroup\$

Usually, the key distinguishing feature of a DSP when compared with a general-purpose CPU is that the DSP can execute certain signal-processing operations with few, if any, CPU cycles wasted on instructions that do not compute results.

One of the most basic operations in many key DSP algorithms is the MAC (multiply-accumulate) operation, which is the fundamental step used in matrix dot and cross products, FIR and IIR filters as well as FFTs. A DSP will typically have a register and/or memory organization and a data path that allows it to do at least 64 MAC operations on unique data pairs in a row without any clocks wasted on loop overhead or data movement. General-purpose CPUs do not generally have enough registers to accomplish this without using additional instructions to move data between registers and memory.

\$\endgroup\$
1
  • 1
    \$\begingroup\$ +1 for the emphasis on MAC operations. These are without a doubt the core of most DSP operations. \$\endgroup\$
    – Matt Young
    Jan 4 '14 at 17:54

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.