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I'm learning the use of configuration statement. For this I've created a top level entity not_gate and an architecture structural. I've also added another vhd file to this program, and that vhd file (notgate) has a single entity and two architectures. I want to choose a specific architecture from the pair. To distinguish between the two, I've decided that the behavioural model of notgate will perform just like a buffer.

not_gate.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity not_gate is
    Port ( NI : in  STD_LOGIC;
           NO : out  STD_LOGIC);
end not_gate;

architecture structural of not_gate is
COMPONENT notgate IS
Port (  invin : in  STD_LOGIC;
        invout : out  STD_LOGIC);
end COMPONENT;
begin
INV: notgate PORT MAP (NI,NO);
end structural;

CONFIGURATION config1 OF not_gate IS
FOR structural
FOR INV: notgate USE ENTITY WORK.notgate(notarch);
END FOR;
END FOR;
END config1;

The vhd file notgate was added to this.

notgate.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY notgate IS
PORT (invin : IN STD_LOGIC;
        invout: OUT STD_LOGIC);
END ENTITY notgate;     

architecture notarch OF notgate IS
BEGIN
invout <= NOT invin;
END ARCHITECTURE notarch;

architecture notbeh OF notgate IS
BEGIN
PROCESS(invin)
BEGIN
IF invin = '0' THEN invout <= '0';
ELSIF invin = '1' THEN invout <= '1';
ELSE invout <= 'U';
END IF;
END PROCESS;
END ARCHITECTURE notbeh;

When I run not_gate.vhd, according to the configuration statement I wrote, the architecture notarch must be selected from notgate.vhd and the NOT operation should occur. However, it seems that vhdl is still selecting the last compiled architecture, that is, notbeh. Thus, the NOT operation doesn't occur. The configuration statement doesn't seem to be working. Could someone tell me where went wrong?

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  • 1
    \$\begingroup\$ Are you absolutely certain that your compiler supports configurations? \$\endgroup\$ – Joe Hass Jan 5 '14 at 12:49
  • \$\begingroup\$ Yeah, which tools are you using? Some have poor or no support for configurations. \$\endgroup\$ – Brian Drummond Jan 5 '14 at 12:56
  • \$\begingroup\$ @JoeHass Xilinx ISE 14.2 Project Navigator that comes with the WEBPack... Its the free licence. I don't know if configuration is supported or not. \$\endgroup\$ – Analon Jan 5 '14 at 15:37
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    \$\begingroup\$ Xilinx ISE has problems with configurations. Move the configuration (which in VHDL is a "design unit" in its own right) into a separate file, and XST (some versions) report "no design unit found" in that file. \$\endgroup\$ – Brian Drummond Jan 6 '14 at 9:32
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I don't have a Xilinx ISE license running anywhere but do have a recent ghdl and gtkwave. After insuring analysis of notgate before not_gate and because ghdl doesn't have an interactive shell for simulation I added a testbench providing stimulus:

library ieee;
use ieee.std_logic_1164.all;

entity test is
end entity;

architecture foo of test is
    component not_gate is
        port ( 
            ni:     in  std_logic;
            no:     out std_logic
        );
    end component;
    signal ni, no:     std_logic;
begin

DUT: not_gate
    port map (ni, no);

STIM:
    process 
    begin
        wait for 5 ns;
        ni <= '0';
        wait for 10 ns;
        ni <= '1';
        wait for 10 ns;
        wait;
    end process;

end architecture;

configuration config2 of test is
    for foo
        for DUT: not_gate
            use configuration work.config1;
        end for;
    end for;
end config2;

I saved your notgate, not_gate and config1 design units and appended the above test bench test all to notgate.vhd. And:

ghdl -a notgate.vhdl

ghdl -e config2

ghdl -r config2 --wave=config2.ghw

gave:

config2 ghw waveform dump for test bench

This tells us two things. 1) Your configuration works and 2) there are alternative tools where configuration works properly.

It tells us a third thing too, that you might need to do without configuration in the particular synthesis environment, but you can separate learning VHDL from a particular synthesis environment.

This was done with a gcc-4.8.2 version of ghdl (ghdl-0.31dev) running on OS X 10.9.1 and using gtkwave 3.3.53 (the OS X app version).

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At least for newer Xilinx FPGAs, ISE 14.7 supports configurations as stated in the XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices on page 39. For older devices it might be necessary to enable the new parser.

But, the configuration must be defined in the declarative part of the archiectture. Thus, the following implemenatation of not_gate uses the notarch architecture as expected:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity not_gate is
    Port ( NI : in  STD_LOGIC;
           NO : out  STD_LOGIC);
end not_gate;

architecture structural of not_gate is
COMPONENT notgate IS
Port (  invin : in  STD_LOGIC;
        invout : out  STD_LOGIC);
end COMPONENT;

FOR INV: notgate USE ENTITY WORK.notgate(notarch);

begin
INV: notgate PORT MAP (NI,NO);
end structural;

The same is stated in the XST User Guide for ISE 14.2, but I cannot actually test it.

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