This is the logic diagram for a MCU that allows for an external clock option via
Tn. This clock can be used as the source for clocking an internal timer register.
According to the datasheet this diagram was extracted from,
"Registers are positive edge triggered. The latch is transparent in the high period of the internal clock. The edge detector generates 1 pulse for each positive/negative (depending on the setting of a register) edge detected."
How does this diagram work? I have tried to search around the net to see what the trapezoid logic symbol represents (in the edge portion) but could only find its meaning with respect to program flow (it represents a mechanical/physical step).
That being said, I am not sure at all how the edge detector works. As for the synchronizer, it appears that the latch (the first flipflop) is only enabled (LE) when
clk is high and the timer value will be passed, but what is the purpose of 2 flipflops?. I understand that the edge detector must enable the output AND gate only when a LOW/HIGH transition is seen at
Tn (and only once period), but I am not sure how exactly this works.
Tn may be equal to or slower than
Tn and they are 180 degrees out of phase? That is, their transitions are at the exact same time. It would seem me that the clocking of the internal timing register would be undefined.