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This is the logic diagram for a MCU that allows for an external clock option via Tn. This clock can be used as the source for clocking an internal timer register.

According to the datasheet this diagram was extracted from, "Registers are positive edge triggered. The latch is transparent in the high period of the internal clock. The edge detector generates 1 pulse for each positive/negative (depending on the setting of a register) edge detected."

How does this diagram work? I have tried to search around the net to see what the trapezoid logic symbol represents (in the edge portion) but could only find its meaning with respect to program flow (it represents a mechanical/physical step).

That being said, I am not sure at all how the edge detector works. As for the synchronizer, it appears that the latch (the first flipflop) is only enabled (LE) when clk is high and the timer value will be passed, but what is the purpose of 2 flipflops?. I understand that the edge detector must enable the output AND gate only when a LOW/HIGH transition is seen at Tn (and only once period), but I am not sure how exactly this works.

Tn may be equal to or slower than clk.

What if clk = Tn and they are 180 degrees out of phase? That is, their transitions are at the exact same time. It would seem me that the clocking of the internal timing register would be undefined.

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    \$\begingroup\$ The trapezoid often represents a mux (multiplexer) in digital logic, but the one you show has no select/address pin. \$\endgroup\$ – David Jan 5 '14 at 16:57
  • \$\begingroup\$ The trapezoid is a MUX. It selects whether the edge detector will respond to the positive or negative edges of the Tn signal pin. The selection term for the MUX comes from "positive/negative (depending on the setting of a register)". The input synchronizer circuit requires that the Tn signal be slower than the internal CLKio. The frequency relationship between the two would be specified in the part datasheet and often specified that Tn is at least lower than 1/4 the frequency of the CLKio. \$\endgroup\$ – Michael Karas Jan 5 '14 at 18:04
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The synchronization block is used to capture a signal that is not synchronous with the system clock (clkio in that example) -- it is required for any synchronous logic and as far as you're concerned it is transparent other than the fact that it delays the signal seen by the edge detector by 2 clock cycles. It prevents an "illegal" (not clearly 1 or 0) from entering the core where it can cause havoc. If you're really curious I can explain metastability and synchronizer chains but for this specific question I think that's overkill.

The edge detector block is simpler. The trapezoidal shape is a MUX, as Michael Karas mentioned. It allows the block to find either rising edges or falling edges. The flip flop is sampling the output of the MUX every clock cycle and essentially "remembering" the last value (1 or 0). The final AND gate is comparing the last value remembered by the flip flop and the inverted current value and will ONLY be high for 1 clock cycle if the signal changed state.

Look at how the output of the flip flop delays the input of the flip flop by 1 clock cycle:

 IN:  0000111100001111000011110000...
OUT:  0000011110000111100001111000...

Now take a look at signal that is the bottom input of the AND gate and the output of the FF above:

INV. FF INPUT:  1111000011110000111100001111...
    FF OUTPUT:  0000011110000111100001111000...

Take a look at the logic of an AND gate:

 A | B | Y
---+---+---
 0 | 0 | 0
 1 | 0 | 0
 0 | 1 | 0
 1 | 1 | 1

One of those inputs is the output of the FF, the other is the output of the inverter... What do you see:

INV. FF INPUT:  1111000011110000111100001111...
    FF OUTPUT:  0000011110000111100001111000...
--------------------------------------------------
 AND GATE OUT:  0000000010000000100000001000...

You get one short pulse every falling edge of the input to the edge detector block (assuming the MUX is routing the non-inverted signal to you). If the MUX selects the inverted signal, you will get a short pulse every rising edge of the input.

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  • \$\begingroup\$ Concerning the Synchronization block: Why is the first latch enabled on high, and the second enabled on rising edge? Why wouldn't they both be rising edge? BTW, I learned a lot from your answer. Thank you! \$\endgroup\$ – Eraticus Jul 22 '17 at 19:30
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The trapezoid is a MUX. It selects whether the edge detector will respond to the positive or negative edges of the Tn signal pin. The selection term for the MUX comes from "positive/negative (depending on the setting of a register)". The input synchronizer circuit requires that the Tn signal be slower than the internal CLKio. The frequency relationship between the two would be specified in the part datasheet and often specified that Tn is at least lower than 1/4 the frequency of the CLKio.

Note also that this circuit only produces the Tn_sync clock for just one edge of the Tn signal at a time - not both edges at the same time.

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