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I've completed a few circuit board layouts before, however this is my first time doing a layout with a oscillator/MCU. After doing some reading (via this site and datasheets) I've come up with the following layout.

Specs:

  • 2 layer board
  • 16MHz crystal (5x3 SMD package)
  • TQFP44 MCU

*Note that local ground connections on the top layer (MCU) are drawn over the silkscreen. This was done in MSPaint to increase readability.

Board Layout

Here are the guidelines that I've tried to follow so far.

  • Minimize distance between crystal and MCU
  • Match trace lengths for Osc_In and Osc_Out pins on MCU
  • Keep load capacitors close to the crystal
  • Place ground pour on bottom layer under the crystal
  • Create local power and ground for MCU/crystal

After doing the above, I have a few questions.

  1. Is this an acceptable layout?
    • Have I completely missed the mark on any guidelines?
  2. At 16MHz, should I be putting a guard ring around the crystal?
  3. Should the load capacitors go between the crystal and the MCU or are they fine where they are at?
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    \$\begingroup\$ A comment on terminology: A crystal oscillator is a four pin device that requires power and ground connections and has a single output pin. It includes a crystal and the oscillator circuit. A crystal is a two-pin (or two active pins - some may be in four pin packages) device that requires external components (most often, a couple of inverters inside a microcontroller) to make a complete oscillator. It appears that you are asking about a crystal, rather than an oscillator. \$\endgroup\$ – Peter Bennett Jan 7 '14 at 0:06
  • \$\begingroup\$ Is this a hobby board? \$\endgroup\$ – dext0rb Jan 7 '14 at 0:29
  • \$\begingroup\$ Others will have better experience with actual pkgs used, but I'd suggest: Minimise loop area in crystal circuit. Minimise total distances xtal to IC. Symmetric xtal to IC positioning. C3 and R12 seem to be unnecessarily pushing xtal away from IC, reducing symmetry, increasing loop area and increasing lead length. X1 could be in against IC with C4.C5 alongside or outside it. All substantially more compact and symmetric. | Guard ring should not be essential at 16 MHz - but hurts little if easily accommodated. \$\endgroup\$ – Russell McMahon Jan 7 '14 at 0:48
  • \$\begingroup\$ @Peter Bennett I've edited the post to correct my mincing of terms. Thank you. \$\endgroup\$ – M.B. Jan 8 '14 at 16:16
  • \$\begingroup\$ @dextorb No, it's not a hobby board but it won't be production either. It's going to a fab house to be made. \$\endgroup\$ – M.B. Jan 8 '14 at 16:30
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At 16MHz matched length traces will not provide any benefit. They key however is to ensure that your GND return paths are short and that the crystal lines are isolated from clocking sensitive traces such as Uart RX or Reset lines, or any other functional traces to which coupled clocking could cause false interrupts or undesired functionality. To the Grounding, I would suggest placing some vias close to the GND paths of the load capacitors rather than relying on the GND trace back to the MCU. I generally place a 0.2/0.4mm via near every signal component ground pad where possible and at least 3 0.4/0.8mm vias for power or transient prone components. The general rule for noise/high speed is to keep your ground impedance as low as possible.

Your layout doesn't indicate whether the polygon pour on the bottom layer is ground, but in the event it is then I would suggest stitching it with some GND vias and applying a polygon GND fill on the top layer once your layout is complete. Try to stitch around any high speed or noise sensitive lines with GND vias.

Also, be mindful of trace-pad exits which are not at 90*. Acute angles between pads and traces will result in "acid traps" during the etching process and in the case of hand etched PCBs, may not etch correctly.

Also consider the local plane for VDD. Larger copper areas will be more susceptible to noise than wide traces with close grounding. I generally prefer to place such power fill on internal layers between GND planes for BGA escape. If your top layer is to be GND filled than this won't be a problem provided it is well decoupled.

Best of luck!

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