I am trying to learn about these things but I have very hard time to understand frequency divider and the leading edge and trailing edge of voltage.

Please, help is needed if someone explain it in easy way. Or could someone route me to any good resource of learning these things.

Currently I am reading the book named "CODE the hidden language of computer hardware and software" but I am stuck at chapter number 14.


Your question is actually pretty vague (without having that book in front of me anyway. You could be talking about digital or analog signals). But since you mentioned a flip flop I'll make the assumption that you're asking about taking a digital square wave of frequency N and realizing a square wave of frequency N/x, where x is an arbitrary number.

A d flip flop can be useful in realizing such a circuit especially if you want to divide the frequency by a power of two. The easiest way to visualize this stuff and get going is imagine a single flip flop with an inverter between the q output and d input clocked by the input square wave in question. The q output would change state (toggle) every other clock. In other words you'd be dividing your input signal by two. You could chain multiple flops together and divide by 4, etc.

That's useful if you want to divide by a power of two, but what about something else? Say, 3? Then you could use a counter and a magnitude comparator to drive the input of a flip flop. In this circuit you could have a free running counter with reset. You'd have a comparator that compares the count value to 2 (3-1 since you start counting at zero). A flip flop would register the output of your magnitude comparator. When that output of the comparator is true you'd get a pulse that's one clock period high. You could use the output of the comparator to reset the counter such that every three cycles you get a pulse. The duty cycle of your output signal wouldn't be 50% anymore (assuming the input signal is), but you'd have a signal that's 3 times slower (or whatever you're using as input to the comparator) than input. This can be really useful for enable logic or something where you want to do something every x cycles.

There are other "fancier" ways to divide a digital signal (or realize an "arbitrary" digital signal from an input one) that involve phase locked loops, DCMs, etc. These are frequently found on FPGAs, micros, and ASICs, but since you're asking the question it's 99.9999% certain that you wouldn't be in a position to build one of these, but rather control its parameters such that you get an output signal that meets your requirements.

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A D flop flop transfers the state of its D input to its Q output at the rising edge of its clock input. A typical D flip flop has Q and a /Q output with the /Q being the NOT Q or inverted Q.

With the /Q output tied back to the D input the flip flop will effectively divide the clock frequency by 2.

It goes... Starting with Q=0, /Q=1, D=1 (tied to /Q). Clock rises, Q :=(gets) D at the rising edge, now the condition is Q=1, /Q=0, D=0 and it stays that way till the next rising edge where Q:=D again which is now 1 so the output toggles. D goes high on the first positive edge then low on the second positive edge of the clock and so on.

Before anyone corrects me, Q and /Q are not always opposite. If the flip/flop has a clear and set pin and both are active, Q is 1 due to set, and /Q is 1 due to clear. Same values.

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  • \$\begingroup\$ I disagree with your statement about simultaneous set and clear. I think one of these inputs will generally override the other and /Q will always be the complement of Q. Now, if you are talking about a simple RS latch it's another matter altogether. \$\endgroup\$ – Joe Hass Jan 7 '14 at 11:58
  • \$\begingroup\$ Here is the datasheet link for the definitive D Flipflop, the 7474. Check the truth table on page 3.i2c2p.twibright.com/datasheet/74HC_HCT74_3.pdf The set and clear inputs are designed to work this way and it's often convenient when doing digital design work such as state machines. \$\endgroup\$ – dfowler7437 Jan 7 '14 at 23:27

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