# difference between using reset logic vs initial values on signals

Let's say I have a signal, I can either assign a initial value of zero OR I can set it to zero upon RESET. I've seen my co-workers using the two method interchangeably. I just want to see others opinion on this.

Assume in my code the flag signal is a flip-flop

Example (using initial value):

architecture arch of xxx is

signal flag : STD_LOGIC := '0';

begin
process (clk) begin
if rising_edge(clk) then
-- do something
end if;
end process;
end arch;


Example (using reset value):

architecture arch of xxx is

signal flag : STD_LOGIC;

begin
process (clk,rst) begin
if (rst = '1') then
flag <= '0';
elsif rising_edge(clk) then
-- do something
end if;
end process;
end arch;

• In the reset case you have a signal to bring the logic back to a known state at any time. Are you just asking for opinions? Jan 7 '14 at 19:24
• Explicit reset is usually preferred for synthesis. If you don't put it in it may get inserted later when it comes time to build the scan chain. Jan 7 '14 at 19:44
• this is really an open-ended question. there are so many ways to bring logic to a known state, and the best way usually boils down to the design requirements. I should have said my question is for FPGA, not ASIC Jan 20 '14 at 19:07

Some comparisons I can think of quickly:

• Initial values on flipflops only work in FPGAs (not ASICs)
• You have to reinitialise the whole device to get back to the FPGA initial values (at least until you start dabbling in partial reconfiguration.) This takes time, whereas a reset takes a single clock cycle.
• You can have a variety of reset signals which allow you to set different parts of the device back to their original setting.
• In FPGAs, you can use initialisers to set the values in a ROM or RAM block - you can't do that with a reset clause.

In the olden days, some FPGA synthesisers just ignored initial values and set everything to initialise to '0', so some FPGA design guidelines still frown on explicit initialisers.

As Joe commented, initial values can seem not to work on signals which are not flipflops, which can cause confusion. This is because (usually) non-flipflop signals are driven by pure logic, which means they take on a value as soon as the simulation starts running based on the inputs to that logic:

 s <= x and y; -- any initialiser will be overwritten by x and y immediately.


An example where this doesn't happen (which is sometimes useful in testbenches, but not synthesisable):

signal s : std_logic := '0';


then

s <= '1' after 100 ns; -- s will be '0' to start with and '1' after 100 ns

• I just wanted to add that initial values only work on flip-flops, even though they are declared as a signal. I think you implied this but sometimes that's a distinction that programmers have trouble with when they start using HDLs. Jan 10 '14 at 16:40
• that's true. I didn't say that I made the flag signal as a ff. Feb 3 '14 at 7:48