# How to determine I2C Master timing parameters

I am relatively new to I2C, but I have done much reading on the topic and I am confused as to the timing parameters necessary when designing an I2C Master.

I know of this chart from the manual on page 48.

However it gives a large range of possible values.

For example, I need to set the following parameters for my I2C Master (using a National Instruments program) in Standard-Mode:

tSU;STA - MIN = 4700 ns
tHD;STA - MIN = 4000 ns
tSU;DAT - MIN = 250 ns
tHD;DAT - MIN = 0 ns
tSU;STO - MIN = 4000 ns
tBUF - MIN = 4700 ns
tHIGH - MIN = 4000 ns
fSCL - MIN = 0 - MAX = 100 kHz


How can I calculate the appropriate values for my I2C bus for all of the above?

Do you always use the minimum, does it matter how many slave devices there are, etc?

• If you want to design robust systems, you design to meet the WORST CASE. Sometimes that's minimum, and sometimes its a maximum. Often, data sheets will give you the worst case (either in the minimum or maximum column, whichever applies), and a "typical value", which is best ignored! – Scott Seidman Jan 8 '14 at 18:24
• Well I am using a National Instruments PXI machine to behave as the Master (this is the part I need the timing for). The device I am communicating with is a MEMs gyroscope. The data sheet for the gyroscope slave simply lists a copy of the above chart for Standard-Mode I2C as well. Does that mean any values would work? Its just hard for me to conceptualize changing a bunch of those numbers and expecting the same result. – MrHappyAsthma Jan 8 '14 at 18:28
• The info on the data sheet should certainly override any information in the I2C standard you've posted from, as there is no real guarantee that the device actually meets the standard (often, the devices might even function BETTER than the standard calls for). That said, I2C is pretty easy to use. Devices can even fix things on their own using clock stretching if the master is trying to go too fast. Pick numbers that looks reasonable, try them, and see if you get expected behavior. It's not like you're carving them in stone. – Scott Seidman Jan 8 '14 at 18:39
• Well I mainly ask because I would ideally like to use a smaller frequency on the clock. If I set the fSCL to say 20 kHz. I wouldn't need to adjust any other numbers? I want to adhere to this statement from the manual: "here are several strategies available to system designers to cope with excess bus capacitance. 1. reduce fSCL" – MrHappyAsthma Jan 8 '14 at 18:42
• Going slower on the clock should not require adjustment of other numbers – Scott Seidman Jan 8 '14 at 19:07