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I'm doing a PCB where there are 3 SMPS: one boost(12v to 48v, 1 amp max) and one buck converter(5v to 4v, 4 amps max) functioning at the same frequency(same timer in microcontroller). the other converter is a synchronous buck(~10v to 8v, at 1 amp). The first pair of SMPS will switch at 400 kHz(perhaps less, if noise becomes too problematic) and the 3rd at 50kHz or less.

Now, I'm having problems designing my board mainly because of: ground bounce issues; interactions between inductors(undesired transformer); cross talk of the current loops in the 4v-4amp buck and the other lower current converters;... I know that the frequencies here are not very high for some of you, however that is still a lot of current at that frequency in my opinion, and I'm hesitant about some strange effects showing up. So, can you give me some pointers about the design of the board? I have enough flexibility with space, but the board only has 2 layers... Ask more details if needed.

edit: the load in the first buck is an electrolyzer; the load in the boost is a led panel; these two loads will be functioning at the same time. the source in the second buck is a fuel cell and the load is an electric toy train. schematic

anymore details I can add?

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    \$\begingroup\$ Do you have a layout (and screenshots) ? That's better than guessing your design. \$\endgroup\$ – zeqL Jan 9 '14 at 15:37
  • \$\begingroup\$ give me an hour. I'll do a schematic. up to now I only tested the converters one at a time, in a bread board(except the 4 amp one, up to the max current) \$\endgroup\$ – mik Jan 9 '14 at 15:39
  • \$\begingroup\$ I take it that the problems you are having are perceived/predicted problems before the event, yes? It is very important to know how the various loads are intended to be connected also. \$\endgroup\$ – Andy aka Jan 9 '14 at 15:41
  • \$\begingroup\$ exactly right. I'll add more details concerning the loads when the schematic is added \$\endgroup\$ – mik Jan 9 '14 at 15:47
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It is difficult to answer you precisely because you are in a pre-design phase and don't have a final schematic.

Thinking about signal integrity and EMC/EMI issues is good, but it is maybe too early to consider them as blocking issues. As a beginner it is difficult to make a "perfect" schematic and layout from scratch. That's why, IMHO, you should provide a schematic and a bit of pre-layout, that we will be able to "correct" (in a good way).

Nevertheless, here is some tips and documents that can help you design your board:

  • If you have space, don't be afraid of adding spare components/PCB footprints

In your case, you could put some spare capacitor and ferrite bead footprints at the output of your SMPS, for future filtering for EMI. If you don't use a parallel footprint (mostly capacitors), you just don't have to solder the component, and for a series component, you can put a 0 Ohm resistor of the same SMD footprint.

  • You are not the first at designing simple SMPS at these frequencies

Having questions is good, but don't be too afraid to make a mistake (if you have the possibility, mostly as student or hobbyist, you are able to do some mistake without "problem"), you will learn more with mistakes than with good (but maybe not so good) design every time. FPGA test board have some 3 to 5 or 6 small SMPS to power the FPGA. Ok they are not on 2-layers PCB but it's not impossible ;)

Finally some documents, guidelines for analog/power design:

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  • \$\begingroup\$ this is very good info. I'll process it and along the weekend probably assemble a primary version of the board so more accurate advice can be given. \$\endgroup\$ – mik Jan 10 '14 at 17:42
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MiB, the location of how you draw the ground links as shown in your schematic will be a very good "visual" for you so you can get an appreciation of where the noisiest ground currents will be and you'll get a feel for how to avoid the subsequent noise. For example, let's look at the loop of current around Q1, D2 and C3. This has a large di/dt during switching. The ground path between Q1 and C3 will thus have an extremely high di/dt so even a few nano-Henrys of inductance will cause large voltage spikes between the two. The ground link to the other circuits should not start on the trace between Q1 and C3 but, on the load side of C3. Likewise, the connecting returns should not branch from the traces between Q1/C3, D1/C9 or Q2/C6. I would avoid a solid ground flooded around everything with a return. Instead, use cutouts to force the high-di/dt currents to flow only to/from the parts like Q1 to a capacitor. Connect to the plane after the capacitors.

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