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I have been trying to simulate a flash ADC in NGSPICE using the gEDA package. I had used the 74148 8 to 3 encoder and the UA741 OpAmp in the model. I had also included the requisite spice model files. However, when I compile the netlist in ngspice, i get the error:

Too few parameters for subcircuit type "74f148" (instance: xx2)

Can anyone help me here?


* gnetlist -g spice-sdb flash_Adc_NationalInstruments_eignd.sch
*********************************************************
* Spice file generated by gnetlist                      *
* spice-sdb version 4.28.2007 by SDB --                 *
* provides advanced spice netlisting capability.        *
* Documentation at http://www.brorson.com/gEDA/SPICE/   *
*********************************************************
*==============  Begin SPICE netlist of main design ============
*UA741 Signetics-TI Corporation
.INCLUDE ./models/UA741.inc
.INCLUDE ./models/74f.lib
R26 6 0 100  
R24 4 0 100  
R22 0 13 100  
R20 2 0 100  
R18 0 12 100  
V4 0 22 SIN(0 10 100kHz)
V2 21 0 100
X34 22 14 Vcc Vee 11 UA741
X32 22 15 Vcc Vee 10 UA741
X30 22 16 Vcc Vee 9 UA741
X28 22 17 Vcc Vee 8 UA741
X26 22 18 Vcc Vee 7 UA741
X24 22 19 Vcc Vee 5 UA741
X22 22 20 Vcc Vee 3 UA741
X20 22 21 Vcc Vee 1 UA741
R16 20 21 100  
R14 19 20 100  
R12 18 19 100  
R10 17 18 100  
R8 16 17 100  
R6 15 16 100  
R4 14 15 100  
R2 0 14 100  
X2 0 1 2 3 4 5 6 7 8 9 10 11 12 0 13 74F148
.end

* 74F148  PRIORITY ENCODER 8-3 LINE
*
* FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS
* Freescale 2010 Model SN74148
* JLS   8-26-92   REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES
*
.SUBCKT 74F148   IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I
+ A0_O A1_O A2_O GS_O EO_O
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
*
UF148LOG LOGICEXP (9,14) DPWR DGND
+ IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I
+ IN0   IN1   IN2   IN3   IN4   IN5   IN6   IN7   EI
+ A0 A1 A2 GS EO
+ D0_GATE IO_F
+ IO_LEVEL={IO_LEVEL}
+
+ LOGIC:
+ IN0    = { IN0_I }
+ IN1    = { IN1_I }
+ IN2    = { IN2_I }
+ IN3    = { IN3_I }
+ IN4    = { IN4_I }
+ IN5    = { IN5_I }
+ IN6    = { IN6_I }
+ IN7    = { IN7_I }
+ EI     = { EI_I }
+ IN0BAR = { ~IN0 }
+ IN1BAR = { ~IN1 }
+ IN2BAR = { ~IN2 }
+ IN3BAR = { ~IN3 }
+ IN4BAR = { ~IN4 }
+ IN5BAR = { ~IN5 }
+ IN6BAR = { ~IN6 }
+ IN7BAR = { ~IN7 }
+ EIBAR  = { ~EI }
+
+ A0     = { ~(EIBAR & ((IN1BAR & IN2 & IN4 & IN6) |
+                       (IN3BAR & IN4 & IN6) | (IN5BAR & IN6) | IN7BAR)) }
+ A1     = { ~(EIBAR & ((IN2BAR & IN4 & IN5) |
+                       (IN3BAR & IN4 & IN5) | IN6BAR | IN7BAR)) }
+ A2     = { ~(EIBAR & (IN4BAR | IN5BAR | IN6BAR | IN7BAR)) }
+ EO     = { ~(IN0 & IN1 & IN2 & IN3 & IN4 & IN5 & IN6 & IN7 & EIBAR) }
+ GS     = { ~(EO & EIBAR) }
*
UF148DLY PINDLY (5,0,9) DPWR DGND
+ A0 A1 A2 GS EO
+ IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI
+ A0_O A1_O A2_O GS_O EO_O
+ IO_F
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ BOOLEAN:
+   DATAHI   = { IN7=='1 & IN6=='1 & IN5=='1 & IN4=='1 &
+                IN3=='1 & IN2=='1 & IN1=='1 & IN0=='1 }
+   ENABLE   = { CHANGED(EI,0) }
+
+ PINDLY:
+   A2_O A1_O A0_O= {
+     CASE (
+       ENABLE & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS),
+       ENABLE & TRN_HL, DELAY(3.0NS,5.5NS, 9.0NS),
+                TRN_LH, DELAY(3.5NS,6.0NS,10.0NS),
+                TRN_HL, DELAY(4.0NS,6.0NS,12.0NS),
+       DELAY(4.0NS,6.0NS,12.0NS)
+       )
+     }
+   GS_O = {
+     CASE (
+       ENABLE & TRN_LH, DELAY(2.5NS,4.5NS, 8.0NS),
+       ENABLE & TRN_HL, DELAY(3.0NS,5.5NS, 8.5NS),
+                TRN_LH, DELAY(2.0NS,4.0NS,10.0NS),
+                TRN_HL, DELAY(2.0NS,6.0NS, 9.0NS),
+       DELAY(3.0NS,6.0NS,10.0NS)
+       )
+     }
+   EO_O = {
+     CASE (
+       ENABLE & TRN_LH, DELAY(3.0NS,5.0NS, 8.0NS),
+       ENABLE & TRN_HL, DELAY(4.5NS,7.0NS,12.0NS),
+                TRN_LH, DELAY(2.0NS,3.5NS, 7.5NS),
+                TRN_HL, DELAY(2.5NS,4.5NS, 8.5NS),
+       DELAY(4.5NS,7.0NS,12.0NS)
+       )
+     }
*
.ENDS
*
*$
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  • \$\begingroup\$ If you don't share your deck, the best we can tell you is you didn't provide enough parameters when you instantaited the 74F148 subcircuit. \$\endgroup\$
    – The Photon
    Jan 10, 2014 at 4:57
  • 1
    \$\begingroup\$ Added the pastebin docs to the question because one of them has a 30 day expiration on it and that would render the question useless in a month. \$\endgroup\$
    – jippie
    Jan 10, 2014 at 7:53

2 Answers 2

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Your subcircuit begins with this card:

.SUBCKT 74F148   IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I
+ A0_O A1_O A2_O GS_O EO_O

Notice, there are 14 connecting nodes, starting with IN0_1 and ending with E0_0.

But when you instantiate the subcircuit, you use this X card:

X2 0 1 2 3 4 5 6 7 8 9 10 11 12 0 13 74F148

This card tries to make 15 connections to the subcircuit, starting with 0 and ending with 13 (node 0 is connected twice).

The number of nodes assigned in the instantiation (X card) must match the number of connections called for by the subcircuit definition.

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0
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I don't think your 74F148 model is a generic SPICE model, it looks like it could be specific to PSPICE. You should check the manuals for ngspice to see if it supports the logic equations and delay statements.

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  • \$\begingroup\$ Is there a resource library specific to ngspice? I have been looking for it and its very crucial for my project. Anyway, thanks for your help! :) \$\endgroup\$ Jan 10, 2014 at 15:54

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