The problem:

Your embedded system has an 8-bit microprocessor, which has a 16-bit address bus. In addition, you have a 32-Kbyte FLASH chip, and a 8 KByte RAM chip. You want to locate the FLASH chip right in the beginning of the address space and the RAM at the end of the address space. All the memory chips have a single /CS selection line, which is controlled by a fast 32 x 8 OTP-ROM chip.

What are you going to program into the contents of the OTP-ROM, and how do you connect it to the microprocessor and the memory chips?

I got only 1.5p out of 6 points by using a solution similar to the picture I attached. The prof told me the following:

"you got one point for the correct OTP-ROM circuit outputs connection and ½ points for connecting address lines a15 and a14 to OTP-ROM circuit. Other than that, the connection was wrong, and the contents of memory were not given/solved at all."

Please help me in this problem. Any advices are appreciated.

From where should I start? And what I should program into the opt-rom? A 32x8 matrix full of ones and zeros?

block diagram of the opt-rom (see the below.):


my attempted (wrong) solution:


  • \$\begingroup\$ I might be confused but how can you decode 32 possibilities from only 2 inputs? \$\endgroup\$
    – dext0rb
    Jan 10, 2014 at 21:01
  • \$\begingroup\$ The way I think is that if you only use 2 inputs, you have only 4 possible memory locations to access in the ROM. You should put your chip select commands at those memory locations. \$\endgroup\$
    – dext0rb
    Jan 10, 2014 at 21:07
  • \$\begingroup\$ The prof may be expecting either that your ROM inputs include memory-request signals from the CPU, or that you decode the addresses sufficiently to ensure that RAM is only selected within a single 8K region (if your RAM is visible at 0xE000-0xFFFF, it would also be visible at 0xC000-0xDFFF). I'm not sure why your diagram uses a 16KB RAM chip. \$\endgroup\$
    – supercat
    Jan 10, 2014 at 21:15
  • \$\begingroup\$ 1. You should have specified which address lines of the OTP were connected, for a 32KB and 8KB devices, you need A4, A3 and A2 of the OTP for 8KB address space granularity. 2. The OTP /CE line should be always '0' (To make sure the Flash and RAM /CS lines are properly driven). \$\endgroup\$
    – Lior Bilia
    Jan 10, 2014 at 21:46
  • \$\begingroup\$ Please do not erase the content of the question. The full text of the question is necessary for proper understanding of the answers and for future visitors who have a similar question. \$\endgroup\$
    – user35419
    Jan 11, 2014 at 20:06

2 Answers 2


I put on my teacher/professor hat.

  • your text mentions an 8Kb RAM, your diagram shows 16Kb.

  • your ROM has 32 locations, hence it needs more than the 2 address lines you connect to it. Even if you intend to connect some lines to a fixed value, you should how that.

  • the question explicitly asks for the PROM content, which you don't give. Yes, it is a 32x8 table of 1's and 0's, but the point is which value you put at each location! You won't need to specify all of the 32x8 locations.

I suggest you draw yourself a memory map. The smallest item you must map is 8Kb, so how many blocks will it have to cover 64Kb? How many address lines are involved in selecting one block? If less than the number required by the ROM, what are you going to do with the others? For each block, note the value of those address lines, and the value of the two select output bits. Now it is almost trivial to write out the content of the PROM. It will contain a lot of "don't care" bits.

Side note: only archaeologists make such systems from separate chips these days, and even micro*controllers* are switching from 8 bit to 32 bit. But the design of something like this is still a good test of your general knowledge of digital logic.

  • \$\begingroup\$ Thank you for your answer. You mentioned that I need to cover 64Kb, how come? My memory consists of the 32Kb FLASH and the 8 Kb RAM, right? That means the memory map would be 32+8=40Kb, and then I'd need 5 blocks to cover it. \$\endgroup\$
    – user35372
    Jan 12, 2014 at 8:30
  • \$\begingroup\$ So if I have 5 blocks, which each consists of 8 bit, and I have 16 bit address lines available, then I'd need 3 address lines (5*8=40/16=2.5). Am I correct? \$\endgroup\$
    – user35372
    Jan 12, 2014 at 8:35
  • \$\begingroup\$ No. And what do you mean by a fractional number of lines? A memory map shows the memory as seen from the CPU. How much memory can your CPU address? \$\endgroup\$ Jan 12, 2014 at 8:50
  • \$\begingroup\$ How much memory can your CPU address? So it addresses 8bit of data trough 16bit address lines, and I have 8 blocks to cover (64/8=8). Does that mean, that I need address lines a15 to a12 connected to ROM and ground the rest? \$\endgroup\$
    – user35372
    Jan 12, 2014 at 9:04
  • \$\begingroup\$ Your first comment above is mostly gibberish, the second makes some sense. But how many address lines do you need to select 1 out of 8 blocks? And next draw that memory map! \$\endgroup\$ Jan 12, 2014 at 9:27

Good answer by @Woutervanooijen. Let me expand a bit on what you got wrong.

The smallest memory device being 8K, you need to be able to assert /CS on 8K boundaries. This means breaking a 64K memory space into 8 blocks. The first 4 are the Flash and the last is the RAM. The OTP ROM needs the micro-processor A13, A14, and A15 as inputs on OTP address lines A0 A1 A2 and ground the rest. Your Dx outputs are fine.

The OTP ROM contents are very simple. The first 4 locations are 11111110 and the 8th location is 11111101. The rest you can leave at 11111111. (Note in your case it can all be XXXXXX01 and XXXXXX10 and XXXXXXX11. Only the least significant 2 bits of data are used).

There are other combinations possible for the ROM. For example you could use the high 3 address lines and duplicate the data entries in 8 groups of 4.

Problems like this are written to be solved and in larger classes they are written to be easily graded by looking for certain key results. The answers are often built into the problem with clues like the RAM size in this case. You are supposed to ask yourself "How much of the OTP do I need? Do I need all 32 entries? What is the smallest block I need to address?" etc. A grader will look for obvious mistakes, like using 0000001 instead of 11111110 to assert /CS.

The 16K device error would get my attention if I was grading. I would look for other papers with the same error because it looks as if it was copied without checking. Many teachers use A and B assignments or tests slightly different to catch that kind of thing.

  • \$\begingroup\$ So THATS why I always sucked at these sorts of tests! I would have connected A15 directly to the CS pin of the flash, then configured the ROM as an inverter, with A15 on the input side and the RAM CS son the output..... ROM in the bottom half of the address space, 4 aliased images of the RAM in the top, it meets spec and would be easier on the PCB layout guy! \$\endgroup\$
    – Dan Mills
    Nov 30, 2019 at 15:02

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