In addition to the previous answers:
Use your timing analysis tool in your FPGA toolchain to find any signals you've forgotten to handle correctly.
You can easily generate a list of unconstrained clock transfers, all of which should be synchronised and an appropriate false-path added. Ideally embed this into your build system so that it fails with an error if there are any unconstrained clock transfers, then you can't forget about them!
Have a single entity/module for doing your single bit synchronisation, use a generic/parameter to control the number of registers in the resync chain. You might want a separate synchroniser for resets.
The advantage of re-using code - embed the false path constraints in the RTL. That way you don't have to remember to add timing constraints for every signal.
A note about placement
Registers in synchroniser chains need to be placed close together to ensure maximum timing window is provided. Altera claim to automatically detect synchroniser chains so they shouldn't need placement constraints. If you're paranoid on Xilinx you can use RLOC constraints to ensure your synchroniser registers are placed close together (unfortunately Altera don't support relative location constraints).