# What does overlaping indicate in i2c timing diagram

I have understood almost every basic concept, like, how the start and end of the transfer occur, what is SDA and SCL and what is master/slave.

but in this timing diagram, SDA supposed to show the transmission of data bits, i do not understand how the two lines of transmission are displaying in the SDA here which are over each other. shouldn't it be a single line for SDA too ? also, what does the dashed line indicating here ?

• You expect the guy who drew the diagram to know what data you want to send? Or to give you a different diagram for sending 0x00, 0x01, 0x02, etc...? – The Photon Jan 11 '14 at 19:45

Not sure if I understand your question but... The dashed lines in your diagram means, more of the same for some time.. like the gap in SCL between 2 and 7 is dashed to mean there are bits 3, 4, 5, and 6 which repeat the same pattern as 1, and 2.

The reason for double lines.. the upper line is for a 1 and the lower is 0, they both are shown as either is valid. For example when SCL transitions at bit 7 in the diagram SDA could be either a 1 or a 0 depending on what you are sending. But.. it must be either a 1 or a 0. Elsewhere where you see the lines crossing, that indicates the signals can be undefined, the state is not determined. This allows time for I/O lines to change.

note that SDA is the data, which is clocked into the part using SCL. SDA must be at 0 or 1 state some time before the clock transition, this is called the setup time. It should also remain in that state for some time after the SCL transition, called the hold time.

• Wow, two other answers entered and voted up twice while I was typing out my answer... – dfowler7437 Jan 11 '14 at 19:52

Where the SDA line is shown with a line at the high and low level at the same time, it means the data could be either high or low (but must remain at that level) during that time period. Whether it's high or low depends on what data you are transferring, and will change from message to message.

Where the lines are shown dashed, it means there are bits of the message that aren't shown because they are similar to the ones that are shown. In this diagram, bits 3, 4, 5, and 6 of the message are skipped over with dashed lines to allow two bytes of message to be shown clearly in the diagram.

Those overlapping lines are for 'visual convenience', the Line(SDA) could either be low or high and together they help to represent the symbol length. A symbol would be either logical one or logical zero.
The dashed line represents a continuity/stream of symbols which will, of-course, vary from application to application( Ex. a 1 byte transfer would involve 8 symbols).