# Deciphering Mux/Demux/Switch Nomenclature: AxB:C?

I'm looking through Digikey's Interface - Switches, Multiplexers, Demultiplexers section (and, thanks to W5VO, the Logic - Signal Switches, Multiplexers, Decoders section as well), and I'm having trouble deciphering what circuit/topology I need.

I've got a processor with a 32-bit coprocessor interface, and I'd like to interface it with a parallel Flash or RAM chip. Ideally, I would have both, and could swap between the two in software. I imagined (wrongly, it appears) that this would be a fairly common need, and that I could buy a pair of ICs that would each break out 16 inputs into 2 banks of 16 outputs, with power, ground, a single channel select pin, maybe an enable/high impedance pin. This would ideally come in a 54-pin TSSOP or 64-pin QFP or something of that size. A 32-switch chip would also work, but I imagine that two switches would make routing the a bit easier. The interface would be digital (I don't really need an analog switch), and I'd like to keep up with the 150MHz maximum speed grade of my processor (but will settle for 72MHz or so of actual performance). I am confident that I don't need some of the $200+ crosspoint switches! I imagined that this would be a simple task, but it seems that my idea of what AxB:C should mean is different from Digikey's idea. I thought that the options would include 1x16:32 or 16x1:2, but (1) these options are not available at reasonable prices (I don't see why this device should cost$70 or $234!), and the other options (like 8x2:1, which seems popular) are designed for analog switching of Ethernet signals. 1. Where can I learn about the mux nomenclature? (An answer on this site would be ideal :) Also, where can I learn about the various functions listed, like AV/crosspoint/Ethernet/USB? 2. What topology or function should I use for to do this task (digital, ~100MHz, 32 or 16 lines)? 3. If all else fails, how can I build a switch out of discrete components or transistor arrays? ## 3 Answers There's a few questions in there, so I'll address them one by one. What does A x B : C Mean? Read this as A instances of a B number of inputs to C number of outputs. What you are looking for, if I understand correctly, is a 16x2:1 or a 32x2:1 chip. If C is more than 1, then your chip is significantly more complicated - you would no longer be selecting one input and connecting it to the output. Which leads well into the next sub-question - Why are there$200+ chips for this simple function?

The specific part you linked is a 1x32:16 wide-bandwidth, DC coupled, buffered, video MUX, which can select any of it's 32 video inputs and output them simultaneously on it's 16 buffered outputs, with a gain of 1-2x. You could sorta think of it as a 16x32:1 with a lot of features. It's got quite a bit more inside than just CMOS switches. It isn't really designed for your function, which is...

How do I connect two memories to a master CPU

The most common method for hooking up multiple memory chips to a driver/controller/cpu is to use a tri-state bus. The address lines drive both chips, and the data bus is shared between all chips. Both chips should have a pin like "output enable", which can be controlled by the CPU. I found this article discussing memory buses at a rudimentary level - it has descriptive images. See Figure 8 for the gist of what I think you want. It is the simplest way of hooking things up, and the way I would recommend if the chips support it.

How would I make one?

Well, I think you were on the right track. CPU buses can be bi-directional, so intercepting the right output enable signal may be risky. The part you were probably looking for was a digital switch, something like this 16x2:1 FET mux. This is the cheapest one at \$1.75 each. Wide bidirectional buses are best handled by ICs.

Note

I would check with the maker of your CPU to look for app notes and reference designs regarding memory buses. That will be the easiest way to see if you're on track.

• If it's bidirectional, why do we need a concept of inputs and outputs? Or, what's the difference between an AxB:C chip and an AxC:B chip? – Kevin Vermeer Feb 1 '11 at 18:33
• Ah, I was looking in 'Interface - Switches, Multiplexers, Demultiplexers' when I wanted 'Logic - Signal Switches, Multiplexers, Decoders' – Kevin Vermeer Feb 1 '11 at 18:36
• Not all MUX topologies are bidirectional. The MOSFET switch ones are, because the switch behaves that same in both directions. Only if a topology is bidirectional can B and C be interchangeable. Normally, a 1:2 circuit is considered a de-mux. – W5VO Feb 1 '11 at 18:42

I think you're confusing terms. It sounds like what you want is to connect a SRAM and Flash to a microcontroller. This has nothing to do with crosspoint switches.

I also see you deleted an answer stating the same about 2h ago; if you care to comment why this is wrong we can try to help you out. Otherwise I believe W5VO has answered your question about nomenclature quite well. (edit: nevermind, deleted by owner appears to me the owner of the answer, not the owner of the question.)

Run the address lines together, the data lines together, tie the RD (read strobe) lines together (if the flash has an OE, tie RD to OE as well). The WR lines should be tied together, and now you should be left with two CS (chip select) lines. Either run these to dedicated output enables on the microcontroller (many have built in address decoders) or build up some select logic that gives you a an OE for accesses to one memory range and another OE for another memory range. There are PLENTY of examples online, and the 74HC138 is a great chip for this. Googling for "memory address decoding" or "chip select decode" or even "microcontroller external memory interface" may get you started.

There are some different ways of going about this (Motorola-style bus vs Intel-style bus) but any book or articles on the older microprocessors or microcontrollers will give you plenty of information.

• Agreed - as I mentioned, this is really the preferred way to do multiple memory banks. – W5VO Feb 1 '11 at 19:25
• The 74HC138 is unlikely to work at the 72MHz desired by the original poster. Still, +1 this answer is perfect, because all the processors I've worked with either (a) run slow enough that many people use a 74HC138 and it works fine, or (b) have dedicated chip select pins. – davidcary Feb 28 '11 at 17:40

I think you are making this too hard. Just run the address and lines to the Flash and RAM in parallel. Then chip select chooses which to access. I assumed NOR flash.

An AV switch is designed for analog signal, so it will have a low impedance and high bandwidth (100's of MHz). Also don't forget that you need to pass the edge rates of the signals, not just the frequency.

A matrix switch can switch any input to any output. That is a more expensive and general than a 8x2:1 which is just 8 of 2:1 switches, i.e., 8 of SPDT switches.

• <_< Somehow, I assumed that I couldn't put Flash and RAM on the same bus at the same time. This is probably what I'll do, but I'll leave the question here because I still want to know what AxB:C means. – Kevin Vermeer Feb 1 '11 at 16:35
• Yes, good digital logic teachers tell the students "don't short output pins, or they will fight each other and cause permanent damage!" dozens of times. And yet there are a few devices seem to contradict that -- they are designed to have outputs shorted together in a "tri-state bus" or "open-collector bus" or "matrix" -- tri-state data buses, tri-state shared-memory multiprocessor address buses, I2C communication bus, multi-drop RS485 bus, LED charlieplexing, keyboard matrix, etc. – davidcary Feb 28 '11 at 17:57