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I've been implementing a hardware module in VHDL for part of my university dissertation and I want to implement it as part of a NIOS II core in my cyclone 2 FPGA. This uses the Avalon interface, what resources can I look at designing a generic module? I have no idea where to start with this part of my project.

I don't know whether my design will be a slave or a master. Can someone point me in the relevant direction on designing the part of my project.

So I want my hardware module to form some extra instructions of the CPU to speed up the execution of a specific algorithm. So that we have some Assembly call in my C program that uses the hardware encryption co-processor.

My hardware module is DES Encryption module, and i'd like some extra instructions so that I can interface a CPU core to my module.

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  • \$\begingroup\$ Have you looked into this document: altera.com/literature/hb/qts/qsys_components.pdf \$\endgroup\$ – FarhadA Jan 13 '14 at 8:37
  • \$\begingroup\$ If it's controlled from the processor you probably want it as a slave. Quartus has some tools for defining a "component" with particular input/output buses that may help you get started. It would help if you described your module a bit more, how much of it is built and what it does. \$\endgroup\$ – pjc50 Jan 13 '14 at 10:55
  • \$\begingroup\$ @pjc50 Thats what i'm unsure about. I'll add some more information so someone could point me in the direction I want to head in. I really don't know. \$\endgroup\$ – Dean Jan 13 '14 at 11:14
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You may want to implement this as a custom instruction rather than mem-mapped peripheral. Get started by reading the NIOS II Custom Instruction Guide. You probably want to implement a 'Multicycle' instruction so that you can take a few cycles to calculate the DES values.

The guide explains how the instruction mnemonics trigger your hardware. The result is multiplexed together with the ALU output and directed to the register file. The example in the guide is a CRC generator, so somewhat similar architecturally.

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