I am studying for ADC Pi, for my Presentation. it uses MCP3424 Chips that uses Delta Sigma ADC.

I know how Successive Approximation ADC Works (on paper).

But how Delta-Sigma ADC Performs the calculation from Analog to Digital. For instance,

If the input Analog voltage is 5volts and the reference voltage is 2.048volts. And I programmed the ADC Pi for 17-bits (3.75 Samples per Seconds)

How these input 5volts will be encoded into digitized form for this very ADC (Delta Sigma / ADC Pi) ????

for instance, let's take an example of Successive approximation ADC , here is what it does,

If there is a 3-bit ADC then and the Reference Voltage is 2volts, then,

2^3 = 8-bits

Now 2volts will be divided in 8 levels.

8/2 = 0.25volts (each level will represent 0.25 volts


000 = 0 -> 0.25 volts
001 = 0.25 -> 0.50
010 = 0.50 -> 0.75
011 = 0.75 -> 1.00
100 = 1.00 -> 1.25
101 = 1.25 -> 1.50
110 = 1.50 -> 1.75
111 = 1.75 -> 2.00

How would i perform such calculation for ADC Pi (Delta Sigma) which is programmed for 17-bit ?

All that i could think of is, The bit size is 17. Reference voltage is 2.048volts 2^17 = 131072

Does that mean there will be 131072 levels ?

So, 2.048/131072 = 0.000007812volts Does that mean each level will represent, 0.0000156 volts ?

Now if the input voltage is 3.3volts the digital output will be,

0.0000156 * X = 3.3volts
X = 211538D
X = 110011101001010010B

Is that right ?

I have tried Googling a lot but couldn't find any basic example for Delta Sigma ADC which is why i eventually posted it here.

Datasheets: ADC Pi: http://www.abelectronics.co.uk/docs/stock/raspberrypi/adcpi2/Datasheet-ADCPiV2.pdf

MCP3424: http://ww1.microchip.com/downloads/en/DeviceDoc/22088b.pdf

ADC Pi Schematic: http://www.abelectronics.co.uk/docs/stock/raspberrypi/adcpi2/schematic.pdf

  • \$\begingroup\$ I've constructed a sigma delta ADC using a spreadsheet and it is quite subtle. Also, if you can find it, TI have a great document on this and also give you a decent example of the decimation filter. \$\endgroup\$
    – Andy aka
    Jan 14, 2014 at 15:46
  • \$\begingroup\$ Similar to this: electronics.stackexchange.com/questions/67552/… \$\endgroup\$
    – Andy aka
    Jan 14, 2014 at 17:47
  • \$\begingroup\$ I don't see how 20/13 can be 7. But yes, 0.0000154V per step. 15 microvolts per step and if the rest of the circuit is designed right, you might get close. Delta sigma is really complicated with a 1 bit A/D, noise shaping digital filters, decimation (not really remove 1 in 10) and multiple stages or orders. It is very clever and requires some very cool signal processing results. @andyaka I would love to see your SS. I have wanted to make a discrete delta sigma for teaching and never succeeded. \$\endgroup\$ Jan 14, 2014 at 18:22
  • \$\begingroup\$ @Andyaka, what does "constructed ... using a spreadsheet" mean? Are you simulating? \$\endgroup\$ Jan 14, 2014 at 19:25
  • \$\begingroup\$ @ScottSeidman yeah simulated, possibly my original words were a little flowery. \$\endgroup\$
    – Andy aka
    Jan 14, 2014 at 19:40

2 Answers 2


Everything you need is in the datasheet for that chip in table 4-2 and 4-4. There is no 17 bit mode, but a twos-complement 18 bit mode. If your gains are set to 1, then

Vref- 1LSB will produce 0b01 1111 1111 1111 1111

-Vref will sample as 0b10 0000 0000 0000 0000

and zero will be all zeros

You must divide Vref by any gain setting other than one you place on the PGA.

Having an 18 bit word come in via I2C means that you'll either be throwing out some LSB's, of reading the data into a 32 bit word. Pay very close attention to pages 23 and 24 so you understand what your data will look like. Since these are twos complement numbers, I recommend SOMEHOW reading them in such that the data is LEFT ALIGNED with your SIGNED 32-bit word, and then you can shift them right if you prefer them right aligned, and the compiler should not have problems dealing with the twos complement format. Note that if you get dealing with twos complement format wrong any numbers that end up negative (even due to noise) will not be handled correctly.


I find this one easy to answer, So I'll try "Now if the input voltage is 3.3volts the digital output will be,

0.0000156 * X = 3.3volts X = 211538D X = 110011101001010010B

Is that right ?" No, Your input signal should be within Vref. Since your Vref is 2.048V,So input signal higher than that will produce full scale result. For 17 bits the highest level will be 1FFFFh and 211538Dh is above the no of levels you can get from 17bit.


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