I've designed a modulo 5 counter (0,1,2,3,4,0,1....) with additional features like BCD to 7-segment-display decoder, the reset switch and the special switch to omit number "3" in the counter.

But the question is, how can I determine whether the circuit is Moore or Mealy machine? Are there any important things I should keep in mind? Any help would be appreciated.

enter image description here

  • \$\begingroup\$ Welcome to EE.SE! Can you clarify the question, please? Do you understand the definitions of Mealy and Moore machines, or are you asking for definitions? If you understand these terms and you designed the machine how can you not know what kind it is...can you be more specific? \$\endgroup\$
    – Joe Hass
    Jan 15, 2014 at 1:10
  • \$\begingroup\$ I assume that the circuit was designed using a hardware description language (VHDL/Verilog) so it would be much easier to read and understand as a code. \$\endgroup\$
    – alexan_e
    Jan 15, 2014 at 8:17

1 Answer 1


First of all, that's a terrible diagram that you want us to analyze — it's essentially unreadable.

The key difference between Moore and Mealy is that in a Moore state machine, the outputs depend only on the current state, while in a Mealy state machine, the outputs can also be affected directly by the inputs.

In your design, the state is embodied by the three flip-flops at the bottom, while the inputs are represented by the two switches. The outputs are the varioius LEDs at the top.

It's clear that both switches directly influence the outputs, so you have a Mealy machine.

In practice, the difference between Moore and Mealy in most situations is not very important. However, when you're trying to optimize the design in certain ways, it sometimes is. Generally speaking, a Mealy machine can have fewer state variables than the corresponding Moore machine, which will save physical resources on a chip. This can be important in low-power designs. On the other hand, a Moore machine will typically have shorter logic paths between flip-flops (total combinatorial gate delays), which will allow it to run at a higher clock speed than the corresponding Mealy machine.


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