The following is asked in the context of Xilinx FPGAs (my experience), but may also apply to similar technologies offered by other vendors.
Background: When writing constraints for FPGA I/O, there are OFFSET IN and OFFSET OUT constraints. The purpose of these constraints, to my understanding, is to provide guidance to placement and route processes to ensure that the timing of the input/output signal relative to the FPGA pin/pad is constrained. For example, without this constraint the tools would be free to route your signal from the pad around the IC 6 times, through 100 levels of logic, and then it finally hits your first register.
There are also constraints offered in the UCF to "suggest" to the tools that a register be packed into the IOB. This places the FF/register in a special (fixed) location, closest to the pad/IO. Short of using some other FPGA hardware mechanism (e.g. IDELAY/ODELAY) there is no way to adjust the timing from the pad to the register, or from the register to the pad (the register site is fixed, the pad is fixed, and the route between them is fixed).
I say "suggest" because there are reasons that the first register may not be packed into an IOB for an input, or the last register may not be packed into an IOB for an output. But for this question, assume that the first/last register actually is successfully placed in the IOB, next to the pad.
Question: Do OFFSET IN and OFFSET OUT constraints add any "value" to a UCF? Do they provide the tools any more information about your design that is needed for the I/O timing to be correct?