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The following is asked in the context of Xilinx FPGAs (my experience), but may also apply to similar technologies offered by other vendors.

Background: When writing constraints for FPGA I/O, there are OFFSET IN and OFFSET OUT constraints. The purpose of these constraints, to my understanding, is to provide guidance to placement and route processes to ensure that the timing of the input/output signal relative to the FPGA pin/pad is constrained. For example, without this constraint the tools would be free to route your signal from the pad around the IC 6 times, through 100 levels of logic, and then it finally hits your first register.

Visually: Offset in and out example

There are also constraints offered in the UCF to "suggest" to the tools that a register be packed into the IOB. This places the FF/register in a special (fixed) location, closest to the pad/IO. Short of using some other FPGA hardware mechanism (e.g. IDELAY/ODELAY) there is no way to adjust the timing from the pad to the register, or from the register to the pad (the register site is fixed, the pad is fixed, and the route between them is fixed).

I say "suggest" because there are reasons that the first register may not be packed into an IOB for an input, or the last register may not be packed into an IOB for an output. But for this question, assume that the first/last register actually is successfully placed in the IOB, next to the pad.

Question: Do OFFSET IN and OFFSET OUT constraints add any "value" to a UCF? Do they provide the tools any more information about your design that is needed for the I/O timing to be correct?

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Do OFFSET IN and OFFSET OUT constraints add any "value" to a UCF? Do they provide the tools any more information about your design that is needed for the I/O timing to be correct?

That is exactly what they are there for. Although you say in your question "assume the register is in the IOB", my point would be that I don't need to care whether the flipflop is packed into the IOB - if those constraints are accurately specified, complete and met by the tools.

Forcing flipflop packing is often a useful way to get the best possible timing, but I still add OFFSET constraints so that if anything goes awry I find out about it.

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  • \$\begingroup\$ As I suspected, thanks. Do you have any strategies to share regarding how you set your OFFSET constraints as a "safety" for when IOB packing fails? Some portion of a related clock period?? \$\endgroup\$ – Josh Jan 17 '14 at 14:08
  • \$\begingroup\$ You set them based on the device you are connected to. You specify what timing you require (taking into account and PCB delays, and adding any extra margin you would like to have), and the tools ensure you meet that timing \$\endgroup\$ – Martin Thompson Jan 18 '14 at 18:28

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