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Could anyone share the internal circuit(transistor level circuit) of GPIO section in a microcontroller?

I am curious to see how a pin can serve as both input or output(of course only one at a time). I understand that there will be switch setting, I would like to see the FET level circuit of the switch indeed!

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    \$\begingroup\$ Most MCU data sheets have that information! \$\endgroup\$ – Leon Heller Jan 19 '14 at 13:45
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    \$\begingroup\$ Yes, lots of people can. You could do this yourself too even you had bothered to open the datasheet. \$\endgroup\$ – Olin Lathrop Jan 19 '14 at 14:41
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    \$\begingroup\$ Insufficient preliminary research \$\endgroup\$ – Matt Young Jan 19 '14 at 15:33
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    \$\begingroup\$ @alexan_e If you want this Stack to be overrun with help vampires, then by all means, allow nonsense like this. Disagree all you want, I will always vote to close questions that show absolutely no research effort. \$\endgroup\$ – Matt Young Jan 19 '14 at 16:47
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    \$\begingroup\$ Insufficient preliminary research \$\endgroup\$ – Nick Alexeev Jan 20 '14 at 18:44
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Okay, here is a block diagram of a typical microcontroller (PIC16F616) I/O pin (Figure 4-1 in datasheet).

Manufacturers do not typically publish transistor-level descriptions of anything complex these days, but we can deconstruct the block diagram with a bit of effort. enter image description here

If you want transistor-level schematics of a D flip-flop, it would be something like this (taken from a 74HC74 datasheet):

enter image description here

Where the T.G. blocks are transmission gates, similar to CD4016.

enter image description here

Inverters and gates, you can look up transistor-level schematics in 4000-series CMOS data sheets such as the 4002 4-input NOR.

enter image description here

Of course on a microcontroller chip there would not be ESD protection networks on internal nodes, so that part of the schematic would not be present.

This is all pretty standard CMOS logic. There are two things that are a bit unusual. One is the P-channel transistor marked "Weak" in the GPIO pin block diagram. It is a "Weak" transistor (it has small physical geometry so Idss is only microamperes when it turns on). It is there to act as a pullup current source (similar to a pullup resistor). As you can see, it's only on when selected (/RAPU global weak pullup enable is true), the input is not in analog mode, the pin is tristated (on a PIC this means that the pin is an input, so we don't waste pullup current into an output), and WPUA (individual port pin weak pullup enable is true).

The diodes shown are a simplified representation of the GPIO pin protection network.

The other critical thing is the non-inverting buffer driving the I/O pin. It is a tristate buffer. When the pin is selected to be an input (TRISA is true), the buffer output is driven high impedance. The schematic will be something like this part of a MC14503 (minus the input inverter, since the input is an ENABLE input not a DISABLE input.

enter image description here

When the ENABLE input is low, both transistor are off, and the pin is no longer driven as an output (on a PIC this occurs when TRISx .. where x is the port number.. is true (HIGH)). A normal inverter has either the "top" (p-channel) or the "bottom" (n-channel) output transistor on at any given time. The tristate buffer has a third state with both transistors off. The fourth possible state (both transistors on, across the power supply) is generally not considered very desirable, and the shown arrangement of gates prevents it from occurring.

That is the only part that gets switched when the pin is selected to be an input or output (see the TRISA output from the latch flip-flop on the top schematic- it only goes to the output buffer enable) . There is no reason to switch the inputs off- they remain connected to the output at all times- since they present negligible load. Similarly, the analog peripherals (if any) are designed so they do not present any load.

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Here is a detailed I/O section of an LPC177x/8x mcu (page 116).
I think its operation in input/output mode (as well as several other features) are self-explanatory

enter image description here

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