# Logic gates q's on unconnected and mid-range inputs and gate output

• Why do TTL integrated circuits assume unconnected inputs to be at logic 1?
• What is fan-in and why is it important in the operation of a logic gate?
• What happens to the gate output of NOT logic gate when its input voltage level reaches from 0.4 V to 2.4 V?
• Is it possible for a gate output to receive current from other sources? If so, what amount of current can it receive?

EDIT: Here are my final answers.

• TTL integrated circuits assume unconnected inputs to be at logic 1 because the main requirement for driving a TTL input is to pull-down the level to near 0 V which takes about 1 mA per input.
• Fan-in is the number of physical inputs on a gate. For example, if you need a 2-input AND gate and you have only one input, you need to add logic. [Thanks for the example, @SpehroPefhany. I need to use AND since we haven't discussed NAND yet.]
• There would be no certain response because it is within the noise margin. No logic gate manufacturer would guarantee how their gate circuit would interpret such signal.
• Yes, it could come from the voltage source and the ground. If the output terminal is connected to the form,er it is called sourcing current; to the latter, switching current.
• Meta text is best avoided in question or answer posts. I would edit it out, but I'm sure you will do so yourself. Also, since there are distinct questions in there, it would be good to post as separate questions, one question referencing another if they are related. Composite questions are frowned upon in StackExchange sites. – Anindo Ghosh Jan 19 '14 at 16:22
• Additionally, this sounds very much like homework. Show us (for each separate question, as Anindo hinted) what you have found out so far. – Wouter van Ooijen Jan 19 '14 at 16:38
• Try reading the wiki article on TTL as a first step - take a good look at the basic ttl circuit diagram and think about how such a circuit works . Why do you think a TTL gate "assumes" a high input when nothing is connected? en.wikipedia.org/wiki/Transistor–transistor_logic – JIm Dearden Jan 19 '14 at 17:09
• @AnindoGhosh, I am expecting that my personal note will be removed before you have done it, I just thought I need to explain why I did it. Thank you, I will take note of that and be more responsible in asking. – ellekaie Jan 20 '14 at 2:58
• @JImDearden: I haven't figured it out fully enough to rephrase it in my own words, but I think that the answer is here: "When all the inputs are held at high voltage, the base–emitter junctions of the multiple-emitter transistor are reverse-biased. A small “collector” current (approximately 10µA) is drawn by each of the inputs. This is because the transistor is in reverse-active mode." – ellekaie Jan 20 '14 at 3:21

Incidentally, it's bad practice to leave TTL inputs floating, you should tie them to $V_{CC}$ through a pullup resistor.
1. Literally midpoint between 0 and 5.0V is 2.5V, which is a valid TTL logic level "1", so the output of an inverter will be low (less than 0.4V with rated load). If you want to know what happens between 0.8 ($V_{IL}$) and 2.0V ($V_{IH}$), you can analyze, simulate or measure it from a typical schematic such as this one for the section of an SN7404 inverter.