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Title says it all.

I'm trying to understand the workings of flash memory technologies, at the transistor level. After quite some research, I got good intuitions about floating-gate transistors, and how one injects electrons or remove them from the cell. I'm from a CS background, so my understanding of physical phenomena like tunneling or hot electron injection are probably quite shaky, but still I'm comfortable with it. I also got myself an idea about how one reads from either NOR or NAND memory layouts.

But I read everywhere that flash memory can only be erased in blocks units, and can only be written to in page units. However, I found no justification for this limitation, and I'm trying to get an intuition about why it is so.

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The best answer I've found to your question is covered at How Flash Memory Works where it says:

The electrons in the cells of a flash-memory chip can be returned to normal ("1") by the application of an electric field, a higher-voltage charge. Flash memory uses in-circuit wiring to apply the electric field either to the entire chip or to predetermined sections known as blocks. This erases the targeted area of the chip, which can then be rewritten. Flash memory works much faster than traditional EEPROMs because instead of erasing one byte at a time, it erases a block or the entire chip, and then rewrites it.

I don't understand why the "in-circuit wiring" allow for bit level programming (switching from 1 to 0) but it might be related to the different way the transitions 1 to 0 is performed (programming via hot injection) compared to 0 to 1 transition (erasing via Fowler-Nordheim tunnelling).

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It's by definition. A flash memory that allows writing individual bits is called EEPROM.

Flash differs from EEPROM in that erasures are done in blocks, rather than individual bits. Because erasing is a relatively slow operation, and must be done before writing, performing the erase in a large block makes large write operations faster, by virtue of erasing a large number of bits in parallel.

Erasing in blocks also allows simplifications to the IC, reducing cost. Economies of scale further reduce cost of flash over EEPROM, as flash is used in great quantities these days for solid state disk drives, while EEPROM is used in much smaller quantities.

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  • \$\begingroup\$ thanks for this answer. Does this line of thought also somehow explain why write operations must be done page-per-page ? \$\endgroup\$ – Gyom Jan 24 '14 at 10:27
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    \$\begingroup\$ @Gyom that's not true of all types of flash. Sometimes the limitation is imposed by the protocol (for example, SATA has no way to write less than 512 byte "sectors"). Depending on the type of flash and protocol used to access it, it may be possible to write just one byte to a block that has been previously erased. \$\endgroup\$ – Phil Frost Jan 24 '14 at 12:57
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You are right in the fact that there's no physical justification for having to erase in block units.

Programming a cell is done by creating an electric field between the bulk and the control gate like shown in fig1, and the same idea is valid for erasing the cell, an electric field in the opposite direction would do the job as shown in fig2. enter image description here However, for constructive reasons, it's relatively complex to generate and use the negative voltage, so the strategy used is the one shown in fig3, by setting a high voltage at the bulk (which is the logic ground reference in the sector). Selection transistors can't be used anymore, only the control gates can be driven low, and this forces a full sector erase.

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  • \$\begingroup\$ Flash memory by definition are erased in block. That's why they are called "flash", because with an erase operation you erase many cells in parallel. Instead in an EEPROM you must do this on a per-byte basis, taking a much longer time. By the way, the erase voltage is split between the bulk and gate voltage (one positive, one negative). It's much easier to invert a voltage, with respect to having to generate and deal with very high voltages. \$\endgroup\$ – next-hack Nov 2 '17 at 15:46
  • \$\begingroup\$ Most chips have many PN junctions that are normally biased in such a way as to not conduct. Would it be possible to bias row and column wires to the voltages needed to erase a chip without any of those PN junctions interfering with things? It would certainly possible to use various kinds of floating wells to avoid problems with such PN junctions, but doing that on a per-cell basis would likely be outrageously expensive. \$\endgroup\$ – supercat Nov 30 '17 at 23:37

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