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This is my first PCB for production, and I'm not sure if I've correctly routed it. Mostly I'm concerned about trace running from pin 5 of IC1 to C3/C4 and how that picks up the +5V, which I've routed going anti-clockwise from the bottom of the board. Should I leave it there (between C3 and C2) or should I move it to the left (between R1 and C4) or does it make a difference?

Schematic

PCB Layout

edit

so based on the comments I had a few problems. I've fixed the mixed up pins on the MOSFET, shortened/fattend the traces, and routed a few things across the back layer and added the ground plane there. I've kept the curved traces, because I'm a freak and I don't care :) Original question still in mind, does the PCB match the schematic?:

schematic, revised PCB revised

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  • \$\begingroup\$ What is IC1 and should the decoupling caps be much closer to its pins is my first thought. Also, is it a 2x sided board? \$\endgroup\$ – Andy aka Jan 21 '14 at 12:36
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    \$\begingroup\$ curved tracks look so unnatural :) \$\endgroup\$ – geometrikal Jan 21 '14 at 12:49
  • \$\begingroup\$ The IC is a capacative touch sensor (azoteq.com/images/stories/pdf/iqs904_datasheet.pdf) It is a two sided board, but I just decided to keep it all on one side. \$\endgroup\$ – user28659 Jan 21 '14 at 12:52
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    \$\begingroup\$ I really don't think you want to ground the unused pins in the micro-USB connector. Put pads there so that they're left floating. \$\endgroup\$ – Dave Tweed Jan 21 '14 at 13:10
  • \$\begingroup\$ They should allow this type of question on codereview.stackexchange.com. The reason is that the PCB drawing is a computer data structure which was produced according to a spec. \$\endgroup\$ – Kaz Jan 21 '14 at 22:32
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It's not ideal. Fatter traces will help. Consider using a 0-ohm jumper or two to improve the layout -- single-sided layouts are often a bit of a challenge (and a trade-off). Your clearance to the copper pour is quite small- especially to the pads.. Usually for manufacturability you want that bigger than the trace-trace and pad-trace clearance (because there is so much of it). Maybe you can push the parts closer together or use a 2 layer board.

Below are observations are on the schematic, not the mapping of schematic to layout.

The MOSFET symbol does not match the pin names so that part is wrong - the drain is grounded assuming the part has the standard SOT-23 layout, and you really want the source to be grounded.


Okay, after your edit that doesn't look too bad. You could fatten up the traces going to the capacitors a bit more.

One slightly subtle thing- you might want to partially slice the ground plane just below the conductor going to the capacitive input so it's only connected to the rest of the plane on the right side, back near the chip. That's because it could wobble around quite a bit relative to the chip ground when the MOSFET switches, and that could get coupled into the input.

enter image description here

It would be nice to fix the schematic symbol for the MOSFET and the rubberband lines, but as far as I can see it shouldn't affect functionality.

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  • \$\begingroup\$ There is room for bigger clearance, no problem. I can also go to two sided if needed. What did you mean about connect between TWO GNDs? \$\endgroup\$ – user28659 Jan 21 '14 at 13:03
  • \$\begingroup\$ No, the pin labeled "Gnd" on JP1 in the layout is really the Gate signal in the schematic. \$\endgroup\$ – Dave Tweed Jan 21 '14 at 13:09
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    \$\begingroup\$ GND on the chip is not connected to the MOSFET source on the schematic (the GND net). Oh, and the MOSFET pin names do not match the symbol. \$\endgroup\$ – Spehro Pefhany Jan 21 '14 at 13:10
  • \$\begingroup\$ BTW, noticing the MOSFET was a huge save. I had been looking at the schematic that way for a while and never noticed it didn't match what I had in the working prototype on my breadboard. \$\endgroup\$ – user28659 Jan 21 '14 at 22:18
  • \$\begingroup\$ @user28659 Sometimes not answering the question is more valuable than the part where it is answered. \$\endgroup\$ – Spehro Pefhany Jan 21 '14 at 22:55
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No, I don't think this layout is good enough. The data sheet isn't very good in terms of PCB layout advice so you have to make a best-guess about the decoupling caps. I'd advise this: -

  1. C1 and C2 up close to the chip with their ground returns taking the shortest feasible distance back to chip 0V/GND
  2. Ditto C3/C4

Noticeable in the data sheet is a note about adding a 100pF to pin 4 for "additional RF immunity". This kind of hints that the power pins will be susceptible without good decoupling and to my mind you've not achieved that. Would it be a big problem to go for a double-sided board with a ground-plane.

Also what is the advise from the manufacturer about routing from the CX pin to the cap sensor? I couldn't find anything in the data sheet (www.azoteq.com/images/stories/pdf/iqs904_datasheet.pdf)

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  • \$\begingroup\$ I can move the IC more to the center to shorten the distance. The whole board is 25x30 and that's about as close as I can have things and still hand solder it later (alpha prototype). There is little advice about the CX pin, but in testing on bread boards, the thing is pretty robust once it settles \$\endgroup\$ – user28659 Jan 21 '14 at 13:00
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    \$\begingroup\$ @user28659 it's the lack of pcb advice in the data sheet that is the concern - it may work perfectly reasonably on the board you've already drawn BUT you can't rely on that. Sometimes experience tells you things need to be a bit better and I'd go for a groundplane for 0V. \$\endgroup\$ – Andy aka Jan 21 '14 at 14:35
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    \$\begingroup\$ Is there any copper on the back? Some board houses will charge you more for single sided copper, all the more reason to make the back a ground plane. \$\endgroup\$ – Matt Young Jan 21 '14 at 16:58

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