I created a clock divider with the code below. i followed steps in prof chu's book.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity clock_divider is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC;--Clock in out_red : out STD_LOGIC);--Reduced freq clock out end clock_divider; architecture Behavioral of clock_divider is constant DVSR : INTEGER := 5000000;--for 1 ms tick at 50mhz clk input signal ms_reg, ms_next : unsigned (22 downto 0); signal ms_tick : std_logic;--tick at every 1ms begin process (clk) begin if (clk'event and clk = '1') then ms_reg <= ms_next; end if; end process; ms_next <= (others => '0') when (reset = '1' or ms_reg = DVSR) else ms_reg + 1; ms_tick <= '1' when ms_reg = DVSR else '0'; out_red <= ms_tick; end Behavioral;
out_red is my reduced freq clock out. Test bench shows clock_out hanging at 0. Can anyone figure out where i went wrong?