There is an eval board for the Xilinx Zynq-7000 FPGA called the Zedboard. When you look at the board you will notice a very interesting pattern of bypass capacitors. The designer has a technical note that explains why he/she thinks this is a good way to do bypass for a board like this.
Are there any flaws in the reasoning behind this bypass capacitor scheme?
Disclaimer: I will not answer my own question, as I really would like other experts from this community to bring their knowledge to the table. But I may do a measurement some day to find more facts - and may blog about it + add that here.