The I2C manual by NXP allows Clock Stretching (holding SCL low) by slave devices in order to have the master wait for them to process data, interrupts and the like. This is all fine and well, although not having a timeout seems questionable.
Now, I wonder whether a master controller can use the same method for example when waiting for the host processor to provide/collect data. For simplicity I only consider a single master setup, although it should not matter.
Edit: For the sake of clarity I am concerned about cases in which during a multi-byte transfer the host processor is not able to provide/collect data to/from the master controller. Issuing a STOP and possibly resetting the slave's state machine (auto-increment counters, 32-bit internal registers, etc.) is not feasible.