Analog-Digital Conversion Clock Prescaling - ATmega328P

Question

I am trying to use the ADC on an ATmega328P clocked at 16 MHz. The datasheet mentions the typical ADC clock frequency range as being from 50 kHz to 200 kHz.

By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.

The prescalers for the ADC clock range from 2 to 128. As I understand it, for remaining 'in the spec' I'd probably require a prescaler of more that 80 i.e. 128.

However, the ADC works for all clock frequencies from CLK/128 up to CLK/4 but not on CLK/2 i.e 8 MHz where it just returns 0x3FF (it is a 10-bit ADC) for all conversions. Is it just because I am running the ADC beyond its recommended maximum or is it something else I need to know about?

ATmega328P Datasheet

Answer 1

It quite clearly says in the data sheet that the ADC clock should not exceed 1MHz. If you break the rules, the behavior is undefined.

It might work, it might not work, it might work only when the moon is full and the temperature is more than 23.7°C or whatever.

Obviously, if your clock is 16MHz, you should not use a lower divider than 16.

Answer 2

In case you are interested to operate the ADC at a high frequency there is an article that shows the bit depth tradeoff for overclocking the atmega adc and an analysis of the adc input stage.

The results of the test show that the effective resolution of the ADC vs clock frequency is like