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I am interfacing a flash memory component (M25P16) to a PIC microcontroller (PIC18F14K22) using SPI. However, I am unable to see any data come through on the slave output line at all (literally nothing, as if the chip wasn't even in the circuit).

Attached is a logic analyzer trace and circuit diagram. The logic snapshot is in attempt to read the device ID with command 0x9E, followed by some empty clock cycles to read the data. As you can see, SO line is dead.

I believe I have set the clock polarity and phase correctly (data is output from PIC on the rising edge of the clock, and the clock is idle-low/active-high. Also, my chip select pin is being held high (via pull-up) during startup and then driven low for the transaction. Clock speed is 500KHz, well below the maximum speed. Write protect and Hold lines are tied to Vcc, which is 3.3V. I have pull down resistors for the data and clock lines to bias them low when idle. Although, I have tried letting the MISO line float, as well, to no avail.

Any ideas? Thanks!

schematic

simulate this circuit – Schematic created using CircuitLab

logic trace

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  • \$\begingroup\$ What is the state of your CKE bit in SSPSTAT and CKP bit in SSPCON1? Short answer, try different combinations of setting and clearing those bits. SPI is a super simple protocol to implement, and most problems go back to those two bits. \$\endgroup\$ – Matt Young Jan 25 '14 at 21:54
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    \$\begingroup\$ Thanks @MattYoung. They are SSPSTATbits.CKE = 1 and SSPCON1bits.CKP = 0; which gives the clock idle low and output on rising edge behavior. I tried cycling through all four options without any luck. \$\endgroup\$ – NateFisher Jan 25 '14 at 22:07
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As far as I can tell, you're doing everything right.

If this were sitting on my workbench, here's the next thing I would do:

On production units, I would make the resistor on MISO a pull-up, rather than a pull-down. Page 37 of the datasheet only guarantees 100 uA on "MISO out high", but over 10 times that current on "MISO out low". The 1.6 mA on "MISO out low" is enough to (dimly) light a high-efficiency LED with an appropriate pull-up resistor to +3.3 V. I find adding LEDs to every questionable signal helps me find problems faster. The 100 uA on "MISO out high" means don't expect the flash chip to work with a pull-down of 33 KOhm or less.

On my test jig (but not on production units), I would temporarily change resistor on MISO changed to weakly pull MISO to around 1.5 V -- that helps distinguish between high (near 3.3 V), low (near 0 V), and tristate (near 1.5 V).

I would re-run the test and make sure the only thing connected to MISO is the o'scope (or logic analyzer) probe and that bias resistor -- not even the PIC connected -- to rule out the possibility that the PIC is somehow accidentally driving MISO to GND.

I would make a custom test program on the PIC that does nothing but select the flash chip, attempt a READ IDENTIFICATION and reads 20 bytes, then deselects the flash chip, and then repeats forever. (It looks like maybe you've already done this).

It's theoretically possible that a PIC chip could be damaged just enough that it gives signals barely strong enough for the logic analyzer to distinguish "0" from "1", but not quite strong enough for the flash chip to distinguish them.

So I might check the voltages by (a) tweaking the custom test program so it runs the CLK at 1 Hz, so I can check each line on the flash chip with a voltmeter, or (b) running the test program at a more typical speed -- 500 KHz or 10 MHz should work fine -- and check each pin with an actual o'scope (not just a logic analyzer).

It's pretty easy to destroy a flash chip so it looks fine under visual inspection, but damaged such that now it won't ever work (always tri-state or always outputs 0).

Perhaps swap the flash chip with an "identical" M25P16 chip on something like the JeeLink and see if the problem follows the flash chip or stays with the PIC chip.

Perhaps re-build the entire circuit with fresh wires, a fresh PIC chip, and a fresh flash chip, and swap the chips around to see if the problem follows the PIC chip, follows the flash chip, or follows the prototype wires.

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  • \$\begingroup\$ Yes, and while playing with the pulling resistors it would be worth verifying that switching between a pulldown and a pullup actually changes the state of the MISO line, ie, that it's not shorted to ground or being driven as an output by a misconfigured MCU. \$\endgroup\$ – Chris Stratton Jan 28 '14 at 19:06
  • \$\begingroup\$ The 100µA you are mentioning are not a limitation - they are the test condition. So the spec guarantees that the ouput voltage doesn't drop more than 0.2V below Vcc when the load at the output is at 100µA. But the load can be higher - you have then just a higher voltage drop (which, given CMOS logic levels, could be 1V). Unfortunately the spec doesn't give any limits... \$\endgroup\$ – hli Jan 28 '14 at 19:55
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If the schematic above is your complete circuit: add a decoupling capacitor (100nF) to the EEPROM (between Vcc and GND), and maybe one to the PIC as well.

The pull-down / pull-up resistors can be removed, though they should not affect the behaviour you see.

The serial data you send to the EEPROM looks good, when compared with what the M25P16 data sheet specifies (on page 9). So I guess its not a SPI problem, but something on the side of the EEPROM.

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  • \$\begingroup\$ Agreed, they could be removed. I originally did not have them, but added them to 'clean' up the logic trace. \$\endgroup\$ – NateFisher Jan 26 '14 at 5:19

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