So the data sheet says that registers cannot be written unless the chip is in standby, however, this seems to suggest that the chip has to be taken out of RX mode to read a packet and clear the RX flags.
This seems a little odd since the TX side of the chip can send up to three packets back-to-back. If a chip TX'd three packets at once and the receiver started processing after the first, the other two would be lost since the receiver wouldn't be in RX mode when the next two arrived.
Is the data sheet overly prescriptive on this point? Is it possible to drain the RX FIFOs while staying in RX mode? Any hands-on experience?