I am dealing with synthesis of verilog sources using Vivado Design Suite 2013.3 tool for the first time. The behavior of my design is correct as verified by the pre-synthesis simulation. My problem is that once I perform the synthesis, the resulting netlist is empty and this is confirmed by the utilization report which shows that anything has been utilized on the board I previously chose. The only thing I can see from the scheme are the ports of the top module of my architecture: Top ports

This is the utilization: enter image description here

I have been told that, since my data source is from outside of my device, I have to set the IOB option in the synthesis settings, but neither the official Xilinx guides are helping me on this.


It's possible that all of your logic is being optimized away. If your lop level module doesn't have any outputs or the outputs it does have don't change state, then all of the logic will be removed by the optimizer as it has no effect on the function. The solution is to route out outputs. For example, if you have an CPU core, try routing out the data bus. Or even just part of it - say, the lowest 8 bits. If there is an issue with the number of pins, simply XORing all of the outputs together and routing the result to a single pin is generally enough to prevent the optimizer from deleting everything.

  • \$\begingroup\$ You were right. Adding some outputs at the top module, the netlist starts getting filled, even if the netlist is not complete with all the components yet. I try to figure out how to fix everything, in the meanwhile thank you. \$\endgroup\$ – camillo_benso Jan 29 '14 at 4:49
  • \$\begingroup\$ And I just got bit by this myself where vivado removed all of the logic in a specific clock domain due to a mis-named clock signal. Whoops! \$\endgroup\$ – alex.forencich Jul 30 '20 at 21:41

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