# cross clock domain databus

I asked a question some time ago about crossing clock domains Design practice crossing clock domains and async signals.

One of the "rules" is to never synchronize multi-bit signal bit-by-bit, because of timing glitches between individual bits.

I have now a design, where I need to cross a multibit signal from a 27MHz domain to a 54MHz clock domain.

I have no more FIFO's left in my fpga, so is there any way to do this without using an async fifo?

Is it possible to synchronize the multibit signal, and set some timing constraint, so I at least get an error if timing is not kept?

• Are the 27 MHz and 54 MHz clocks related to each other in some way, through a divider or a PLL? If so, it isn't really a fully asynchronous domain crossing, and different (simpler) rules apply. – Dave Tweed Jan 27 '14 at 14:45
• The 27 and 54MHz clocks are unrelated. – JakobJ Jan 27 '14 at 15:39

You still have to take the necessary precautions on the single-bit synchroniser chain (at least 2 registers placed close together). You may also find that a greater number is required since the false path allows the fitter to physically place the two multi-bit registers far apart. You may need to use a delay constraint to limit the placement (set_max_delay on Altera or define_path_delay on Xilinx).