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I asked a question some time ago about crossing clock domains Design practice crossing clock domains and async signals.

One of the "rules" is to never synchronize multi-bit signal bit-by-bit, because of timing glitches between individual bits.

I have now a design, where I need to cross a multibit signal from a 27MHz domain to a 54MHz clock domain.

I have no more FIFO's left in my fpga, so is there any way to do this without using an async fifo?

Is it possible to synchronize the multibit signal, and set some timing constraint, so I at least get an error if timing is not kept?

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  • \$\begingroup\$ Are the 27 MHz and 54 MHz clocks related to each other in some way, through a divider or a PLL? If so, it isn't really a fully asynchronous domain crossing, and different (simpler) rules apply. \$\endgroup\$ – Dave Tweed Jan 27 '14 at 14:45
  • \$\begingroup\$ The 27 and 54MHz clocks are unrelated. \$\endgroup\$ – JakobJ Jan 27 '14 at 15:39
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If the throughput of data transfers is low then you can use a simple handshake to perform the clock domain crossing:

CDC Diagram

Your launch side places the data in a register and inverts a single bit flag. The flag is synchronised into your latch clock domain and the inversion is detected indicating that there is new data to be re-registered into the latch clock domain.

The latch clock domain inverts another acknowledge bit which is then synchronised back into the launch clock domain, informing the launch side that it can send another word of data.

You still have to take the necessary precautions on the single-bit synchroniser chain (at least 2 registers placed close together). You may also find that a greater number is required since the false path allows the fitter to physically place the two multi-bit registers far apart. You may need to use a delay constraint to limit the placement (set_max_delay on Altera or define_path_delay on Xilinx).

Obviously the rate at which you can transfer words is much less than using a dual clock FIFO. You say you have 'no more FIFOs' left but remember that both Altera and Xilinx support small FIFOs composed from special logic blocks (MLABs in Altera parlance or SLICEMs in Xilinx speak).

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if the two clocks are generated from the same DCM without phase shift, it might work if you use the slower clock as a clk_en signal, only because the fast_clock = 2*slow_clock.

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