# How can I simulate contamination delay in VHDL?

Propagation delay is simple to implement:

  Out <= '1' after 3ns;


I tried to add contamination delay as such:

Out <= '1' after 3ns;
Out <= 'X' after 1ns;


so that Out would become undefined and then switch properly. However, in simulation I only observe the final assignment. [I'm using MultiSim to simulate, but this Quartus II link suggests it's normal to only observe the final assignment]

Is there a good way to simulate contamination delay?

Out <= 'X' after 1 ns, '1' after 3 ns;