I am describing a system in VHDL. This system already contains a processor, a DDR SDRAM controller and a VGA controller. VGA reads pixels from SDRAM (already validated and proven in FPGA).
Although VGA and SDRAM are already communicating with each other, I still need to implement the connection between the processor and SDRAM. In the end, what I intend to have is a processor that draws in the framebuffer stored in SDRAM. Then, a page flip occurs and VGA starts to fetch the new picture that was drawn by the processor.
To instruct the VGA to fetch from the new location, I would like to inform the VGA controller (using memory mapped io) the new address of the new image. A simple strategy that I though was to put a mux and verify if the address range falls on the VGA controller's registers or in the cache's address range. Also, would I need to care about different clock domains? If yes, what possible problems should I care about?
For example, sometime in the past I saw code from x86 that writes (using outb instruction) and the next instruction was a inb to the same and/or a related location. In this case, would I need to modify the processor logic to stall on such operations? If yes, how many cases to implement? How many interfaces to care about?
Also, at bootup, how cache is used if all entries are invalidated? I believe there is a ROM image with the startup code. Could it also exist a temporary local RAM for writings made by code stored in ROM (sw instructions)?
Resume: I need information on how to implement memory hierarchy circuitry: caches, memory mapped io, TLBs, virtual memory etc. And how all this communicate together with each other. I know how to implement caches and TLBs, for instance. But I am not sure on how to connect them together. I could just use something that works (like the mux idea). But I want to follow designs that are established in industry.
What I've already studied: - how to run mips - computer architecture (Patterson) - MIPS manuals - ARM's manuals - Intel's manuals
But none explains in detail.
If there are many ways to implement, just show me one that you know of, please. Even if it is source code or a block diagram. Again, I don't need the explanation of how it works internally. I just need to know the interfaces between the modules.
Thank you all