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I am describing a system in VHDL. This system already contains a processor, a DDR SDRAM controller and a VGA controller. VGA reads pixels from SDRAM (already validated and proven in FPGA).

Although VGA and SDRAM are already communicating with each other, I still need to implement the connection between the processor and SDRAM. In the end, what I intend to have is a processor that draws in the framebuffer stored in SDRAM. Then, a page flip occurs and VGA starts to fetch the new picture that was drawn by the processor.

To instruct the VGA to fetch from the new location, I would like to inform the VGA controller (using memory mapped io) the new address of the new image. A simple strategy that I though was to put a mux and verify if the address range falls on the VGA controller's registers or in the cache's address range. Also, would I need to care about different clock domains? If yes, what possible problems should I care about?

For example, sometime in the past I saw code from x86 that writes (using outb instruction) and the next instruction was a inb to the same and/or a related location. In this case, would I need to modify the processor logic to stall on such operations? If yes, how many cases to implement? How many interfaces to care about?

Also, at bootup, how cache is used if all entries are invalidated? I believe there is a ROM image with the startup code. Could it also exist a temporary local RAM for writings made by code stored in ROM (sw instructions)?

Resume: I need information on how to implement memory hierarchy circuitry: caches, memory mapped io, TLBs, virtual memory etc. And how all this communicate together with each other. I know how to implement caches and TLBs, for instance. But I am not sure on how to connect them together. I could just use something that works (like the mux idea). But I want to follow designs that are established in industry.

What I've already studied: - how to run mips - computer architecture (Patterson) - MIPS manuals - ARM's manuals - Intel's manuals

But none explains in detail.

If there are many ways to implement, just show me one that you know of, please. Even if it is source code or a block diagram. Again, I don't need the explanation of how it works internally. I just need to know the interfaces between the modules.

Thank you all

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  • \$\begingroup\$ Shame this question hasn't got attention. Could you elaborate a bit? Share some of your code? Concrete interfaces? \$\endgroup\$ – Dzarda Jan 29 '14 at 13:06
  • \$\begingroup\$ Sure! Here is the sdram interface: link. It is a simple interface with support to three clients. The first client (client0) has priority over the others. The others are selected by round robin. Clients only need to provide the initial address, how many bytes to read or write, and a buffer where the sdram controller fetches or write. \$\endgroup\$ – hdhzero Jan 31 '14 at 22:21
  • \$\begingroup\$ @Dzarda, here is the VGA's interface: vga. It is attached as client0 in sdram, so reads to VGA are priority. \$\endgroup\$ – hdhzero Jan 31 '14 at 22:24
  • \$\begingroup\$ Here is the processor's interface: processor. The processor is a 2 issue VLIW (a project of mine, with custom instruction set). Although the names appear as dcache and icache, it is only connected to some block rams attached in order to verify in FPGA. \$\endgroup\$ – hdhzero Jan 31 '14 at 22:30
  • \$\begingroup\$ Very interesting. Care to answer your own question since its been 11 months? \$\endgroup\$ – lm317 Jan 15 '15 at 23:18
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Here is a link to a short explanation of how Memory mapped I/O operates in an older style computer system. Perhaps this can answer a few of your questions:

http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/IO/mapped.html

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After all this time, I haven't found anything detailed about the subject. I decided to just code something that would work and forget how the industry does. This was after reading some documentation on the Wishbone bus project that says that in FPGA they use a bunch of multiplexers to create the routes between the modules.

My advise for those who are trying something similar in FPGA: just do something that work. I may be wrong, but there is simply no detailed information around on how to do this kind of stuff.

First of all, I've accepted my reality: I am a FPGA guy, generally limited by clocks of 50MHz. I am also not projecting a system to interface with a motherboard or PCI or whatsoever. It is a simple SoC and all the physical interfaces that I need (keyboard, mouse, VGA, SDRAM, etc) are there, ready for me to use through pin assignments (of course, I still have to implement the logic in VHDL).

In other words: I just need to care about VHDL because the physical stuff is already done by the Altera/Xilinx/YourVendorHere guys.

I'll explain briefly how I did:

  • I didn't implement a bus. At first I wanted to use a bus because it is how its done in general. But the truth is that a bus is only useful if you're going to plug'n play modules and this was not my case (please correct me if I am wrong). So in the end I just used a bunch of multiplexers to map the addresses.

  • For status/control/data registers within modules, I decided to use a simple 'protocol' that you can think as a handshake/polling: in a loop I keep reading the register until it delivers the value I expect, then I perform the operation I want.

  • I have no idea how the ARM and Intel guys do their stuff, but here I simply added a ROM and RAM (both block ram) for bootstrap code. It is simple and it works.

  • The interface between the processor and cache/tlb/mmu is the following: cache, tlb and mmu do not take action by themselves. If there is a miss, it is the processor that has to instruct them to fetch the necessary data.

There are so many details that I don't know what should be explained or not. If any of you need detailed information on how I did things, just mail me: hdhzero@gmail.com. I'll be glad to awnser anything here on stack or in my email.

I'll also let here some links that helped me: http://www.st.ewi.tudelft.nl/~gemund/Publications/michel_bsc.pdf http://amir-shenodua.blogspot.com.br/2012/06/simple-memory-management-with-vhdl.html

I also recommend the following book, that has some chapters describing how one can interface a processor with IO modules: http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317

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