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In my schematic, I have 4 SPI devices to hook together. I am going to operate the SPI up to 8MHz. Should I be concerned with installing damping resistors? source termination resistors? Should I route them in a star formation, or in a serial fashion? Does adding lots of vias hurt the signal integrity?

I also have to add that these devices are quite close together, within 25mm of each other.

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From a signal integrity perspective, 8MHz isn't actually that fast so you can probably get away with any reasonable layout. You might want to include termination resistors in the layout. If you don't need them you can just install 0 ohm resistors and then leave them out in the next revision. I would lay out (star versus serial) with whatever gives you the tighter layout (e.g. shorter traces). Stubs are considered a bad thing for high speed layout, so I'd pick one or the other and not have some scheme where some parts are tied together serially and others are branched off from that. When laying out in a serial fashion, keep the stubs off the main lines as short as possible. Adding vias does hurt signal integrity, but as I mentioned, you most likely have such a large timing budget at 8Mhz that it does not matter. The other question is, do you have a ground and power plane? If so, you want to keep the signals referenced to the same plane (e.g. don't run the SCLK trace on one side of the board referenced to the ground plane and then via to the other side and run for a while referenced to the power plane). You'll probably have to worry about EMC issues here long before you'll have to worry about signal integrity issues, but EMC may not be a concern for you project.

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    \$\begingroup\$ The clock frequency doesn't really matter. Its the rise-time and fall-time of the edges that will determine signal integrity and EMC concerns. If not using slew rate control and using a transceiver that can operate much faster than 8Mhz, say maybe 50Mhz you can have all the signal integrity and EMC issues that you would have at 50Mhz even though the buses clock rate is much lower. A common way to deal with this is to use a transceiver with some level of slew rate control or use external components to slow down the rise/fall times. \$\endgroup\$ – Mark Feb 7 '11 at 18:05
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    \$\begingroup\$ @Mark, The rise time drives EMC issues, but not necessarily integrity issues. The timing budget is so large at 8Mhz that you can have all types of EMC issues without any signal integrity issues because the signals will steady before the clock latches the data. My guess is he has near 20ns of margin here. Of course, if the problem is so bad that the clock is getting double latched or something, he may have issues, but baring a horrible layout, not likely. At higher frequencies termination and layout become much more important for integrity, but most people don't even think about it for SPI \$\endgroup\$ – bt2 Feb 8 '11 at 0:03
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    \$\begingroup\$ In general, why (In 4-layer PCB with ground and power plane) migrating from one side of board to the other, by via that cause changing reference from ground plane to power supply can cause EMI? \$\endgroup\$ – mohammadsdtmnd Apr 9 '19 at 6:52
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It depends on the edge rate. If it is driven by a fast general-purpose chip, e.g. a FPGA, then you might care. But at 25 mm you are ok unless the rise time is so very fast.

As @bt2 said, vias hurt signal integrity, but I wouldn't worry about it at this distance.

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