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schematic

simulate this circuit – Schematic created using CircuitLab

If this circuit is a part of a 4 bit full adder, where A1,B1 are adder inputs and C1 is carry in from previous bit, does C2 give the correct output for the carry out bit? According to my calculations C2 doesnot, although S1 generates the correct value of the sum. Please, I need a cross-check.

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  • \$\begingroup\$ please add your truth table that demonstrates the ins and outs of this logic... \$\endgroup\$
    – old_timer
    Commented Jan 30, 2014 at 14:16
  • \$\begingroup\$ What's with all the inversions? Try drawing it and debugging it with all positive logic to begin with, then apply DeMorgan's Law transformations as needed. \$\endgroup\$
    – Dave Tweed
    Commented Jan 30, 2014 at 15:02

1 Answer 1

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This circuit is more complicated than necessary, but it looks like C2 does give the correct output. The simplified expression for C2 is: $$ C_2 = \overline{\overline{(A_1+B_1)}+(\overline{C_1} \cdot \overline{A_1B_1})}\\ =(A_1+B_1)\overline{(\overline{C_1}\cdot\overline{A_1B_1})}\\ =(A_1+B_1)(C_1+A_1B_1)\\ =C_1A_1+C_1B_1+A_1A_1B_1+A_1B_1B_1\\ = C_1A_1 + C_1B_1 + A_1B_1 $$

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