Is it possible to set a STD_LOGIC_VECTOR(6 DOWNTO 0) with a constant like so:

signal s1: std_logic_vector(6 downto 0);
s1 <= 12;

Or do I have to define it as a set of bits?


2 Answers 2


You can do it, but not directly. Something like this should work:

s1 <= std_logic_vector(to_unsigned(12,7));


s1 <= std_logic_vector(to_unsigned(12,s1'length)); 

Of course at the begining of your file you should declare:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
  • \$\begingroup\$ And of course, if you are representing numbers, you should be using either the un/signed vector types, or an integer type. \$\endgroup\$ Jan 31, 2014 at 14:51

wzab's answer is precisely what you asked. So I'll just remind that you can go the other way round. You could declare s1 as an integer, say:

signal s1: integer range 0 to 127;

and that will keep your code free from type conversions, at least until you have to push the signals out of the chip. Depending on the amount of operations, this can make your code significantly cleaner.


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