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I seem to be having trouble with my board when it is not powered. I have a TI ADC128S02 (datasheet) acting as a slave and communicating with another master board via SPI. There are buffers on the digital lines (Fairchild 74AC541MTC) between the master board and the slave.

My issue is that the master board could potentially be powered without the slave and the ADC being powered. If the master board is powered and sending SPI signals to the unpowered ADC128 then it will damage the ADC's ESD protection circuitry and no longer work correctly.

I'm looking for a way to ground the SPI lines on the slave board when the slave board isn't powered. Once the board is powered the SPI will be operating at 1MHz 5V CMOS logic.

The power analogue and digital power supplies to the ADC need to be isolated and are from different sources, this is to ensure no performance degradation. At the moment when the board is powered off but the SPI is still on this causes V_A = 0.8V and V_D = 1.8V. The datasheet for the ADC states that V_D < (V_A + 0.3V), because this limit is exceeded the device is then damaged.

I was hoping that when the buffer isn't powered the SPI signal wouldn't be seen on the ADC but this is not the case. I thought about using transistor inverters on the SPI lines but I'm worried these will cause signal delays and unnecessary increase in current consumption.

A reduced version of the schematic is included below.

ADC connection to external SPI

The analogue circuitry of the ADC is powered by ARef. The digital side and the buffer are powered by a seperate 5V. The SPI_MISO line is an output from the ADC to the SPI master and is therefore reversed on the buffer. The other three SPI lines are all from the SPI master. None of the ADC inputs have been shown, nor the rest of the connections on the connector.

Any suggestions as to how I can ground the SPI lines when there is no power on the slave board would be greatly appreciated.

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  • \$\begingroup\$ Wouldn't it be that the 74AC541 will bear the brunt of the problem? Maybe I'm missing something? Is the 541 not on the same power rail as the ADC device? \$\endgroup\$ – Andy aka Jan 31 '14 at 18:01
  • \$\begingroup\$ I was hoping that is what the 541 would do but it doesn't seem to have that effect. For some reason when the 541 is not powered an attenuated signal still passes through. The 541 is on the same power rail as V_D on the ADC. \$\endgroup\$ – Bink Jan 31 '14 at 22:14
  • \$\begingroup\$ That's a bugger. I'd not expect that. Maybe double check? \$\endgroup\$ – Andy aka Jan 31 '14 at 22:26
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Route the slave board Vcc to the inter-board header (via a series resistor); if slave Vcc is not present on the header, the master holds its SPI (CS, SCK, MOSI) outputs in Hi-Z.

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  • \$\begingroup\$ This certainly would be a solution but unfortunately I'm not sure we will be able to add an extra line on the J1 connector as all the pins are currently in use. We could remove some functionality of the device to use a line for the Vcc but I would prefer to find some other solution. \$\endgroup\$ – Bink Jan 31 '14 at 22:23
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If CS only went low for a few microseconds, maybe you could use it as remote power from the slave board - the few microsecond drop-out could be ignored by a diode and local Vcc capacitor. If the volt drop were a little too much thru the diode maybe you can have a local Vcc resortation boost converter on board?

Re-arranged - use CS as a power feed from the slave - I believe it's probably active low so although when high it's feeding juice to the ADC and 541, it should be able to sneak low for the regular CS time. If, when high, the voltage is a little too low for powering the chips either make it a little higher feeding in or put a booster on it.

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