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I came across the statement in a digital design book that "nMOS transistors pass 0's well but pass 1's poorly" and "pMOS pass 1's well but 0's poorly".
What exactly do these statements mean and why is it so? Also, what is the reason that AND and OR gate can't be simply formed but they have to be formed as AND=NAND->NOT and OR=NOR->NOT?
This is actually two unrelated questions:
"nMOS transistors pass 0's well but pass 1's poorly" and "pMOS pass 1's well but 0's poorly". What exactly do these statements mean and why is it so?
An enhancement-mode MOSFET conducts best when its gate voltage is significantly different from the channel voltage. The exact value is known as the "threshold voltage". For an N-channel device, the gate needs to be positive, and for a P-channel device, the gate needs to be negative.
Most logic is based on a single (positive) supply voltage, with "1" represented by Vcc and "0" represented by ground. Therefore, an N-channel device can only be turned on strongly when the gate is high and the channel is low ("0"). A P-channel device can only conduct strongly if the channel is high and the gate is at ground, which makes it negative with respect to the channel.
Also, what is the reason that AND and OR gate can't be simply formed but they have to be formed as AND=NAND->NOT and OR=NOR->NOT?
The basic logic element in CMOS is the inverter, with one N-channel device that pulls the output down and on P-channel device that pulls it high. You can create more complex logic functions by putting additional devices in parallel or in series with the basic inverter transistors, but in every configuration, the "active" level of the output is opposite from that of the input(s). Therefore, to create "positive logic" in CMOS, you must always have two stages, where the second stage is usually just an inverter that has good drive characteristics for high fanout.
