Say we have 16 bit processor and such CISC instruction:

0001 0010 0100 1000

As far as I understood from the answer on related question

In the process of decoding, this CISC instruction will be split into single hardware instructions.

  1. Does this mean that the size of each small instruction is always the same. Like the 16 bit CISC instruction will be split onto 4 small instructions of 4 bits?

From the link above:

"...more convenient to implement them as a series of elementary instructions that are contained in a very fast internal memory."

  1. Does that mean that small instruction inside CISC instruction (0001 for example) is an address of an internal memory of a CPU that contain like 16 bit (or something) single instruction which then goes to decoder which creates a signal for ALU?
  • 1
    \$\begingroup\$ "In the process of decoding, this CISC instruction will be split into single hardware instructions" - this might be true for modern Intel-style chips, but it certainly not a universal truth. \$\endgroup\$ Feb 1, 2014 at 12:37

1 Answer 1


To understand the behaviour of the CPU you need to know how an instruction is made: there is a fixed part that represent the instruction (let's say that 0001 stands for INC), that is repeated every time you write an INC instruction, and there is a part that depends on the instruction and it's why the CISC processors instructions are not all long the same. The second part contain, in our example, the address of the memory location that we want to increment (0010 0100 1000, assuming that it uses 12 bits to address the memory).

Every instruction set is made in this way. The difference in the instruction set between a CISC and a RISC processor is that the latter uses an instruction set with a fixed instruction width.

The datasheet of a microprocessor can show you exactly how every instruction is made. If you want to see an example of how an instruction is made I advise you to start with old processors datasheet because they are less complex and are easier to understand. Take a look at the Z80 Datasheet, from page 101.

Coming to the question, essentially no. The CISC instruction does not contain the single microcoded instructions, but only a code that identifies the operation we want to do and the necessary data (value to load, address of the memory location...) to execute the instruction. The CPU has a decoder that when read the code knows what to do for that specific instruction and, if it's a microcoded instruction, it knows how to decompose it. As you can see the number of microcoded instructions in which an instruction is divided isn't depending on the lenght of the instruction and it's something "hidden" in the CPU itself, not accessible from the outside. The same goes for the opcode of the "micro" instructions.

This is a simplistic answer, but it tell you essentially how the things works. You can immediately see why the decoder of a CISC processor, particularly if it uses microcode, like the x86 CPUs, is much more complex than its counterpart RISC.


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