I am a software developer (using high level languages like .NET,C,C++ etc) trying to understand how computers work at a lower level. I never studied any Electrical Engineering at university. I did GCSE Electronics.
I understand conceptually what a clock tick is i.e. tick-phase (low), followed by a tock-phase (high).
Say I have a simple circuit like this:
Is tick when the current leaves negative and tock when it reaches positive?
Imagine a square pulse.
There are the 'high' and the 'low' state.
There are also 2 edges. The rising edge(transition from low to high) and the falling edge(transition from high to low).
Some inputs are edge triggered, while some are triggered by the state of input.
You can know that by their symbol.
The above flip flop's clock is edge triggered, denoted by the triangle and activates on rising edge. The other inputs, S and R, are determined by their state, ie. high and low.
While the above's clock uses the falling edge, denoted by the circle.
So the ticks and tocks are different for each device.
To answer your actual question succinctly: NO.
You are conceptually out in Left Field here. You need to pose the question in terms of logic levels. Logic levels are associated with logic devices: gates, flip-flops, counters, etc.
If you read up a little on logic devices and logic states, I think you will be in a better position to understand what is meant by a "clock" and the terminology associated with its composition. (I.e. Tick Phase, Tock Phase, Rising Edge, Falling Edge, Period, Duty Cycle and Frequency).
Although many modern computers use a one-phase clock, I think that conceptually it's easier to understand what's going on electrically if one thinks in terms of a two-phase clock (the 6502 microprocessor which was used in many computers from the late 1970's to early 1980's was a prime example of a system that used a two-phase clock). The 6502 works with two clock signals. If a 6502 is running at 1MHz, then during each microsecond, the first (called phi1) will be high for about 450ns and go low for 50us while the second just sits low, then the second (phi2) will go high for 450ns and low for 50 while the first sits low.
The use of the two clock phases may perhaps best be understood with a simple example: an 3-bit counter. A three-bit counter will have a total of six latching circuits--half operated off phi1 and half operated off phi2. Call the phi1 circuits X0, X1, and X2; the phi2 circuits Y0, Y1, and Y2. Their behavior is as follows:
When phi1 is high:
X0=Y0
X1=Y1
X2=Y2.
Otherwise
X0, X1, and X2 keep outputting their present values.
When phi2 is high:
Y0 = not X0
Y1 = X0 xor X1
Y2 = X2 xor (X0 and X1)
Otherwise
Y0, Y1, and Y2 keep outputting their present values.
Notice that the X latches are only dependent upon values from Y latches, and Y latches are only dependent upon values from X latches.
Suppose that phi1 is about to go high, and Y2..Y0 hold 000. Then when phi1 does go high, X2..X0 will latch 000. If any Y values were to change while phi1 was high, those changes would be reflected in the values latched for X, but Y values can only change when phi2 is high, and it won't be high while phi1 is high. Some time after phi1 goes high, it will go low again; X2..X0 will continue to hold 000.
Then, some time after that, phi2 will go high. At that point, Y2..Y0 will be fed 001. If any X values were to change, the Y values would also change, but X values can only change while phi1 is high, and that won't happen while phi2 is high. Thus, Y will capture the value 001 and keep holding it even when phi2 goes low.
The next time phi1 goes high, X will capture 001 and keep holding it while phi1 goes low. Then when phi2 goes high, Y will capture 010 and keep holding that while phi2 goes low. Then X will capture 011, Y will capture 011, then X will capture 100, then Y will capture 100, etc.
Note that provided phi1 and phi2 are never high simultaneously (or within a gate-propagation time of each other), each sequence of phi1 going high and then phi2 going high will increase the count by one. If phi1 and phi2 were ever high simultaneously, then the value being fed into X change as the value of X changed, and likewise for Y, and the circuit would most likely behave in unpredictable fashion. Provided that X and Y are never high simultaneously, however, the circuit will count regularly, like clockwork.
Indeed, clockwork might be a good analogy, since a typical clock escapement mechanism will have a sprocket and a couple of pegs which can block its rotation. During parts of each "tick", both pegs will be placed so as to block the sprocket's rotation, but during other parts, one of the pegs will be clear of the sprocket but the other will block it. The pegs block rotation at different points, so that when the first peg is lifted, the wheel can rotate to the next point that the second peg would hit it; when the first peg goes down again, it doesn't affect anything but when the second peg is lifted the wheel can turn a little bit to the point where the first peg hits it. Each up-down cycle of the pegs allows the wheel to turn exactly one click, but if both pegs were lifted simultaneously the mechanism would spin out of control.
In practice, two-phase clocking isn't used in most logic designs because it requires maintaining and running two clock signals all over the place. Further, unless logic can be nicely partitioned into two halves of roughly equal complexity, or unless one could generate clock phases of unequal lengths, the length of each clock phase would be limited by whichever phase was more "complicated"; much of the time in the opposite clock phase would be "wasted". Because in many cases one of the clock phase's circuitry would do nothing but pass through the signals latched by the other, many circuits today use logic elements called "flip flops", or "flops" for short.
A flip flop effectively takes in a single clock signal and generates two clock phases internally. Phi1 is high whenever the input clock is high and phi2 is low; phi2 is high whenever the input clock is high and phi1 is low. Thus, the first stage will sample its input whenever the clock is low and has been for a little while, and the second stage will sample the output of the first stage whenever the clock is high and has been for a little while. If phi1 and phi2 are generated in one place and distributed system wide, reliable operation will require that no device see phi2 go high until every device has seen phi1 go low, and vice versa. Having every flop generate its own phi1 and phi2 means that when generating phi2 it doesn't have to worry about whether every device has seen phi1 go low, but merely whether it has done so itself. That allows the circuitry to be simplified to the point that it's often cheaper to run one clock wire to a latch and have it generate the clock phases internally, than it would be to run two separate clock wires.
If a circuit's logic would naturally lend itself to partitioning into two groups, using a split-phase clock may allow the circuit run faster than would otherwise be possible, but if it does not lend itself to such usage, split-phase clocking will be slower. Because many designs don't lend themselves to such partitioning, designs based on single-phase clocking are much more common, but split-phase clocking can still be useful in some high-performance applications where logic can be partitioned into well-balanced groups. Because it's generally easier to reason about single-phase-clocked designs, split-phase clocking is generally only used nowadays when it could offer sufficient benefit to justify the extra design effort.
