# Which pins sense collisions at 100BaseT?

## Background

Suppose I have the following situation...

• PC with the NIC hard-coded to 100Mbps, Full-duplex
• RJ45 cable, pinned EIA-568B (not that the colors in the pinout matter)
• Cisco Catalyst 3560 Switch, using IEEE 802.3-1998 autonegotiation (10/100Mbps, only)

Since the PC's NIC is locked at 100/full, the Cisco's Ethernet autonegotiation fails and it falls back to 100/half. Now there is a duplex mismatch on the line. Now, let's assume the PC and the Cisco both transmit at exactly the same instant.

  LOGICAL DIAGRAM
===============

Tx                  Tx
100/full          ----->              <-----      100/half
PC        -------------------------------------  Cisco Catalyst 3560

PHYSICAL LAYER
==============

Tx D1              Tx on Rx D2??
----->              <------
568B                                       568B
Pin  Signal                                Pin  Signal
1   TX+ D1    ---------------------------  3   RX+ D2
2   TX- D1    ---------------------------  6   RX- D2
3   RX+ D2    ---------------------------  1   TX+ D1
6   RX- D2    ---------------------------  2   TX- D1

<------
Tx D1


CSMA/CD's flowchart looks like this...

My questions are specifically at the decision block for "Is some other station transmitting?" How exactly does this work at the physical layer?

### Questions:

• Consider the PHYSICAL LAYER diagram. When the Cisco transmits at 100/half, is it only transmitting on pins 1 and 2 (marked Tx D1)? Intuition says this is true, but I want to be sure I understand how a 100BaseT Ether PHY's CSMA/CD works. I consider it possible that half-duplex would configure to transmit on all four pins (Tx D1 and Rx D2) since I have heard that the tx line driver inspects the transmitted signal to look for collisions.
• If the Cisco only transmits on 1 and 2 (Tx D1), does the Ether PHY register the collision because it senses the PC's transmit on pins 3 and 6 (Rx D2)? To me, it's counter-intuitive to register a collision if you have a dedicated Rx pair.